Abstract
In this paper MIS equivalent electrical circuit of Au/Pd/Ti-SiO2-GaAs has been analyzed by a comparison of the results obtained from admittance and DLTS spectroscopy. Two groups of peaks with different magnitude and different gate voltage dependence have been observed in DLTS and admittance spectra. Based on the analysis of the peaks behavior, it has been concluded that they are associated with the response of bulk traps and interface states, respectively. In order to characterize bulk traps and interface states responsible for the occurrence of two groups of peaks in normalized conductance spectra we have used the equivalent circuit with two CPE-R branches. The time constant values estimated for both peaks from admittance analysis have been compared with the time constant determined from DLTS analysis. Some discrepancies have been noted between the time constants obtained for interface states whereas the time constants for bulk traps were compatible. It has been also demonstrated that when conductance peaks overlap, the admittance experimental data can be fitted by the equivalent electrical model with only one CPE-R branch. However, in this case incomplete information about the analyzed process has been obtained despite the fact that all model validity criteria can be fulfilled and the model seems to be correct.