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A High-Gain, High-Bandwidth, Bidirectional Discrete GaN-Based SyncFET dv/dt Sensor for MHz Power Converters Cover

A High-Gain, High-Bandwidth, Bidirectional Discrete GaN-Based SyncFET dv/dt Sensor for MHz Power Converters

Open Access
|Nov 2025

Figures & Tables

Figure 1.

Traditional capacitor-based dv/dt sensor circuit for dv/dt control in GaN devices. GaN, gallium nitride.

Figure 2.

Proposed synchronous capacitive dv/dt sensor circuit for dv/dt control in MHz frequency GaN devices. GaN, gallium nitride; MHz, megahertz.

Figure 3.

The proposed SyncFET dv/dt sensor and AGD for turn-on dv/dt control. AGD, active gate driver; GaN, gallium nitride; SyncFET, synchronous GaN field-effect transistor.

Figure 4.

Simulated VGS_sync waveforms of the SyncFET circuit at different VCC voltages. SyncFET, synchronous GaN field-effect transistor.

Figure 5.

Simulated feedback current waveforms: (a) output from the 0.1 pF capacitor-only dv/dt sensor and (b) output from the 0.1 pF capacitor sensor enhanced by the proposed SyncFET circuit. SyncFET, synchronous GaN field-effect transistor.

Figure 6.

Simulated waveforms of the resultant currents generated by the proposed AGD at different VCC voltages. AGD, active gate driver.

Figure 7.

Comparison between simulated waveforms of the gate currents at different operating conditions.

Figure 8.

Simulated VDS waveforms of the low-side GaN half-bridge under different operating conditions. GaN, gallium nitride.

Figure 9.

DC–DC buck converter test PCB (photograph). GaN, gallium nitride.

Figure 10.

Measured VGS waveform of the low-side GaN half-bridge at 4.5 V and 10 MHz. GaN, gallium nitride.

Figure 11.

Measured VDS waveform of the low-side GaN half-bridge during turn-off at 10 MHz. GaN, gallium nitride.

Figure 12.

Measured VDS waveform of the low-side GaN half-bridge during turn-on without dv/dt control. GaN, gallium nitride.

Figure 13.

Measured VDS waveform of the low-side GaN half-bridge during turn-on with the proposed dv/dt control. GaN, gallium nitride.

Figure 14.

Comparison of measured VDS waveforms of the low-side GaN device during turn-on with and without the proposed dv/dt control. GaN, gallium nitride.

Prototype circuit components, parameters and measurement set-up

NameParameter
Bus voltage (DC)24 V
Operating frequency10 MHz
Main transistors100 V (EPC2106)
Current mirror transistors100 V (EPC2106)
SyncFET100 V (EPC2037)
Reverse transfer capacitance (CRSS)0.5 pF
Sensing capacitor (CS)0.1 pF (Vishay VJ0402D0R1VXBAJHT)
Degeneration resistor (RS)4 Ω
Charge pump circuit supply (VCC)2.5 V
Gate drive voltage (vDRV)4.5 V
Gate resistor (RG)7 Ω
Gate driver IC200 V (Texas Instruments LMG1210)
Load inductor3.5 µH (Würth Elektronik 744771003)
Load current (iL)120 mA
OscilloscopeUNI-T UPO3352E (350 MHz 2.5 GSa/s)
ProbeUT-P08A (350 MHz)

Comparison of PON_loss for different dv/dt regulation techniques

TechniqueRG (Ω)PONloss (mW)dv/dt (V/ns)
Without dv/dt735.9617
Increasing RG1361.7911.12
Capacitor-only dv/dt control754.0311
SyncFET dv/dt control755.7810

Comparative performance analysis of the proposed work and previous studies

Circuit parametersRelated literature
Proposed work
Sun et al. (2016)Bau et al. (2020)Liu et al. (2023)Yu et al. (2023)Yang et al. (2024)
Power switchGaNGaNGaNGaNGaNGaN
Bus voltage300 V50 V300 V400 V200 V24 V
Operating frequencyNot reported1 MHz1 MHz1 MHz1 MHz10 MHz
Sensor capacitance47 pF (discrete)2 pF (discrete)Not reported (parasitic CDS)Not reported (parasitic CDS)Not reported (integrated)0.1 pF (discrete)
Gain amplification methodGate current controlWidth/length ratio adjustmentWidth/length ratio adjustmentWidth/length ratio adjustmentComparatorSyncFET
Flexibility of gain amplification methodHigh (discrete voltage follower)Low (integrated CMOS)Low (integrated LDMOS)Low (integrated high-voltage LDMOS)Low (silicon-on-insulator)High (discrete N-channel GaN SyncFET)
AGD implementationDiscreteIntegratedIntegratedIntegratedIntegratedDiscrete
Switching loss reduction1.86%15.85% @ 20 pF CSNot reported16.2%33.99%16.7%
Response time>2 µs<1 nsNot reported<3 nsNot reported<1 ns
dv/dt regulation8.8 V/ns6.3 V/ns14.3 V/ns63.7 V/ns22 V/ns10 V/ns
DOI: https://doi.org/10.2478/pead-2025-0025 | Journal eISSN: 2543-4292 | Journal ISSN: 2451-0262
Language: English
Page range: 357 - 373
Submitted on: Aug 18, 2025
Accepted on: Oct 15, 2025
Published on: Nov 10, 2025
In partnership with: Paradigm Publishing Services
Publication frequency: 1 issue per year

© 2025 Bright K. Banzie, Francis B. Effah, John K. Annan, published by Wroclaw University of Science and Technology
This work is licensed under the Creative Commons Attribution 4.0 License.