A High-Gain, High-Bandwidth, Bidirectional Discrete GaN-Based SyncFET dv/dt Sensor for MHz Power Converters

In conventional configurations, a capacitor-based dv/dt sensor regulates the switching profile of power devices, particularly in GaN circuits, by producing a feedback current proportional to the dv/dt during switching transients (Figure 1). This current is then supplied to the AGD to modulate the switching behaviour.

Figure 1.

Traditional capacitor-based dv/dt sensor circuit for dv/dt control in GaN devices. GaN, gallium nitride.

The inherent gate-drain capacitance (C_GD) generates current i_CM (see Eq. (1)) due to the drain-source slew rate dvDSdt \left( {{{{d_{{v_{DS}}}}} \over {{d_t}}}} \right) . This approach has been successfully demonstrated in laterally diffused metal-oxide-semiconductor (LDMOS) transistors, whiutilise their inherent capacitances to measure dv/dt. However, GaN devices, unlike LDMOS, pose challenges for dv/dt sensing due to smaller parasitic capacitances and rapid switching, which introduce noise and instability. To enhance feedback current (i_FB) in GaN devices, an external sense capacitor C_S is added, generating i_FB as shown in Eq. (2): (1) iCM=CGD⋅dvDSdt {i_{CM}} = {C_{GD}} \cdot {{{d_{{v_{DS}}}}} \over {{d_t}}} (2) iFB=±G.Cs⋅dvDSdt {i_{FB}} = \pm G.{C_s} \cdot {{{d_{{v_{DS}}}}} \over {{d_t}}} where G is a tunable feedback gain. During turn-on, G is negative, and during turn-off, it is positive. In practice, the sensing capacitor (C_S) is selected to be much smaller than the GaN device’s reverse transfer capacitance (C_RSS), typically <10 pF. As a result, increasing C_S to achieve higher current gain is impractical for GaN power converters. Therefore, dv/dt sensors for GaN must employ high gain to produce adequate feedback currents.

The proposed synchronous capacitive dv/dt sensor builds upon the conventional capacitor-based approach by incorporating a GaN field-effect transistor (SyncFET) configured as a common-source amplifier (CSA), as illustrated in Figure 2, thereby significantly enhancing the feedback gain.

Figure 2.

Proposed synchronous capacitive dv/dt sensor circuit for dv/dt control in MHz frequency GaN devices. GaN, gallium nitride; MHz, megahertz.

The SyncFET dv/dt sensor circuit was constructed using four main building blocks: a CSA stage, a charge pump network, a source degeneration resistor and the sensing capacitor.

The goal is to convert the high dv/dt at the switch node into a strong, controllable current signal that can be used for active dv/dt regulation. During switching transients, C_S generates a current proportional to the voltage slope at the drain of the low-side GaN FET (see Eq. (2)). This current flows into the source terminal of the SyncFET, which operates as a voltage-controlled current source. A charge pump maintains a constant gate voltage (V_{G_sync}) above the device threshold (V_TH), determined by the supply voltage V_CC, which is referenced to the system ground. This biasing ensures that the SyncFET remains in the saturation region during operation. Since the source voltage (V_{S_sync}) varies with the transient current from the capacitor sensor, the GS voltage (V_{GS_sync}) also varies dynamically, producing a modulated drain current (i_sync).

The SyncFET thus acts as a current amplifier. The drain current, i_sync, becomes the sensor output, feeding into the high-output-impedance AGD, which acts as an active load. This configuration achieves high current gain while voltage gain remains negligible. The current gain (A_i) of the SyncFET stage is given in Eq. (3): (3) Ai=ΔisyncΔVIN=gm×VGS_syncVGS_sync=gm {A_i} = {{\Delta {i_{sync}}} \over {\Delta {V_{lN}}}} = {{gm \times {V_{GS\_sync}}} \over {{V_{GS\_sync}}}} = gm where V_IN = V_{GS_sync} represents the sensor input voltage, and gm denotes the transconductance of the GaN device.

To improve linearity and control the gain, a source degeneration resistor, R_S, is introduced, modifying the effective input voltage as shown in Eq. (4): (4) VIN=VGS−syncIS×Rs {V_{IN}} = {V_{G{S_ - }sync}}{{\rm{I}}_{\rm{S}}} \times {{\rm{R}}_{\rm{s}}} where I_S is the current through R_S.

The resulting effective current gain is shown in Eq. (5): (5) Ai=ΔIDΔVIN=gm1+gm×Rs×VINVIN=gm1+gm×Rs {A_i} = {{\Delta {I_D}} \over {\Delta {V_{lN}}}} = {{{{gm} \over {1 + gm \times {R_s}}} \times {V_{lN}}} \over {{V_{IN}}}} = {{gm} \over {1 + gm \times {R_s}}}

This gain can be tuned by adjusting V_CC or R_S, keeping V_{GS_sync} within the safe operating limit for GaN devices (typically <6 V). The bidirectional nature of the GaN SyncFET ensures symmetrical response to positive and negative dv/dt transients, making the sensor suitable for high-speed dv/dt sensing during transients in MHz-frequency power converters.

This paper addresses turn-on dv/dt control in MHz GaN converters, a critical factor in addressing issues such as crosstalk, EMI, device stress and reliability (Bau et al., 2020). While turn-off dv/dt is also important, in GaN devices it causes minimal energy loss due to high transconductance and short crossover time (Lee et al., 2016). Although this paper focuses on turn-on dv/dt control, it is useful for turn-off dv/dt control as the proposed SyncFET dv/dt sensor circuit allows for bidirectional dv/dt sensing.

Figure 3 illustrates the proposed dv/dt sensor connected to an AGD. While Figure 2 presents the standalone SyncFET-based dv/dt sensor circuit, Figure 3 shows its integration with a modified GaN-based current-mirror AGD as proposed in Banzie et al. (2025). In this configuration, the amplified feedback current generated by the dv/dt sensor is injected into the AGD input stage, enabling closed-loop regulation of the turn-on transition. This combined setup highlights how the sensor circuit interfaces with the gate driver to achieve practical dv/dt control in MHz GaN converters.

Figure 3.

The proposed SyncFET dv/dt sensor and AGD for turn-on dv/dt control. AGD, active gate driver; GaN, gallium nitride; SyncFET, synchronous GaN field-effect transistor.

During turn-on, a rapid negative dv/dt across the capacitor dv/dt sensor induces a negative current (i_CS), which flows out of the source of the SyncFET. This lowers the V_{S_sync}, thereby increasing the V_{GS_sync} (as V_{GS_sync} = V_{G_sync} – V_{S_sync}); V_{G_sync} is a fixed positive voltage set by the charge pump circuit. The increase in V_GS induces i_sync, governed by the transistor’s transfer characteristics in the saturation region, and flows into the AGD opposite to the i_CS (see Figure 5). Implemented as a cascode current mirror topology employing four discrete n-channel GaN devices, the AGD offers high impedance and high bandwidth, avoiding significant capacitive loading on the gate while enabling fast, precise control (Banzie et al., 2025). The current mirror stabilises the SyncFET’s output and effectively mirrors the amplified dv/dt-induced current.

Figure 4.

Simulated V_{GS_sync} waveforms of the SyncFET circuit at different V_CC voltages. SyncFET, synchronous GaN field-effect transistor.

Figure 5.

Simulated feedback current waveforms: (a) output from the 0.1 pF capacitor-only dv/dt sensor and (b) output from the 0.1 pF capacitor sensor enhanced by the proposed SyncFET circuit. SyncFET, synchronous GaN field-effect transistor.

During turn-on, a portion of the driver current, i_S, is injected into Q₅, increasing its drain current i_D5 and voltage V_D5. Since the equivalent output resistance seen by Q₅, R_D5 is small, V_D5 ≈ V_GS (GS voltage of the main GaN device). The total sink current applied by Q₅ is shown in Eq. (6): (6) iR5=iS+iFB {{\rm{i}}_{{\rm{R}}5}} = {{\rm{i}}_{\rm{S}}} + {i_{FB}} where i_R5 is the resultant sink current, i_S is the sink current derived from the driver output, and i_FB is the feedback current due to the SyncFET dv/dt sensor. Simultaneously, the rise in V_D5 raises the source voltage of Q₃, reducing its GS voltage (V_GS3) and biasing it into third-quadrant mode. This produces a second sink current i_R3 from Q₃, flowing opposite to i_FB but contributing to gate current reduction. The combined dv/dt control law is provided in Eq. (7): (7) iG=iDRV−iR5+iR3 {i_G} = {i_{DRV}} - \left( {{i_{R5}} + {i_{R3}}} \right) where i_G is the net gate current and i_DRV is the driver’s source current. The SyncFET therefore enhances the current-sinking capability of the AGD, improving dv/dt reduction during turn-on. The SyncFET dv/dt sensor with the AGD addresses the following key CSA limitations:

• The Miller effect is minimised by GaN’s small C_GD, boosting bandwidth.

• Low C_GS and C_DS reduce capacitive loading, improving frequency response.

• Source degeneration improves linearity and bandwidth by reducing gain.

• Active load (AGD) provides high output impedance, increasing the gain-bandwidth product and current transfer efficiency.

The proposed SyncFET–AGD circuit was first evaluated in simulation to validate its dv/dt control capability before hardware prototyping. Simulations were conducted in PSpice using manufacturer-provided GaN transistor models that incorporate parasitic capacitances and gate charge dynamics. The set-up replicated the test circuit parameters summarised in Table 1: a 24 V DC bus, 10 MHz switching frequency, EPC2106 GaN half-bridge as the main device, EPC2037 SyncFET, TI LMG1210 driver integrated circuit (IC), 3.5 μH load inductor and 120 mA load current. A 0.1 pF external sensing capacitor and 4 Ω source degeneration resistor were employed to implement the proposed dv/dt sensor. The simulation was run under steady-state conditions, and dv/dt was extracted during turn-on transitions for comparison with experimental measurements.

The circuit was validated at 10 MHz, representative of emerging industrial GaN-based converter applications (Chen and Ma, 2021; Li et al., 2019; Wang et al., 2020; Yan et al., 2020). While lower frequencies simplify the design due to reded parasitics, higher frequencies demand tighter PCB layout control. The 10-MHz benchmark aligns with emerging industrial trends and provides a practical test case.

Simulation validation using PSpice models with estimated parasitics is followed by hardware implementation on a custom four-layer PCB. Signal and power traces are routed on the outer layers, with inner ground planes minimising loop inductance. An EPC2106 GaN half-bridge is used for switching, chosen for its compact layout and reduced parasitics. Gate drivers and decoupling capacitors are positioned close to the half-bridge to limit inductive effects.

The dv/dt sensor targets the low-side GaN FET, using a 0.1 pF sensing capacitor to ensure high bandwidth and minimal loading. The EPC2037 is selected as the SyncFET for its fast-switching characteristics and low input capacitance, while a 4 Ω source degeneration resistor balances gain and stability. Supporting components are placed tightly around the sensing node to maintain signal integrity. A 2.5 V supply ensures that the SyncFET operates within safe GS limits.

The AGD employs a modified cascode current mirror built from two EPC2106 half-bridges to enhance mirroring accuracy and high-frequency performance. Component values were optimised through simulation sweeps and experimentally validated, as summarised in Table 1. Despite a nominal 24 V input, turn-off transients can push V_DS up to ∼43 V (Figure 11), so both EPC2037 and EPC2106 are selected for their 100 V rating to ensure reliability under MHz switching.

The prototype is realised using discrete GaN FETs (EPC2106, EPC2037), a commercial driver IC (TI LMG1210) and off-the-shelf passives (e.g. Vishay, Würth inductor). While this discrete implementation increases printed circuit board (PCB) footprint and cost compared with monolithic driver ICs, it offers modularity, higher breakdown margins and flexibility for MHz operation. Looking ahead, with ongoing GaN IC integration trends, the SyncFET–AGD concept could be embedded into driver ICs, reducing cost and improving manufacturability. AGD, active gate driver; GaN, gallium nitride; MHz, megahertz; SyncFET, synchronous GaN field-effect transistor.

Simulation validates the proposed SyncFET–AGD combo for turn-on dv/dt regulation. As shown in Figure 4, increasing V_CC to 5 V causes V_{GS_sync} to exceed the GaN device’s safe operating limit (6 V) and introduces oscillations due to parasitic interactions between the sensing capacitor and device capacitances. This shows the importance of carefully biasing the SyncFET; while higher V_CC increases sensor gain, it also risks instability and device overstress. Therefore, V_CC must be maintained <5 V for safe, stable operation.

The proposed sensor responds to both turn-on and turn-off transients, confirming its bidirectional dv/dt sensing capability. However, since the AGD is currently optimised only for turn-on control, turn-off dv/dt suppression remains a direction for future work.

In Figure 5, significant feedback current amplification is observed from the 0.1 pF capacitor when using the SyncFET during turn-on. This gain scales with V_{GS_sync}, and while higher gain improves sensing, it also narrows the safe operating range of V_CC. This trade-off reflects the balance between sensitivity and reliability that is common to capacitive dv/dt sensors. Despite the amplification, the sensor current remains smaller than the primary gate drive current, confirming the need for additional amplification through an AGD stage, consistent with earlier findings by Sun et al. (2016) and Bau et al. (2020).

As shown in Figure 6, increasing V_CC also enhances the AGD output currents i_R3 and i_R5, improving current mirroring accuracy and extending the effective control range. Figure 7 illustrates improved gate current shaping when the SyncFET is integrated with the AGD. The combination introduces an active ‘soft charging’ mechanism at the gate during turn-on, effectively emulating a larger Miller capacitance. This dynamic shaping slows the charging of C_GD, directly reducing dv/dt at the switching node. Figure 8 confirms this effect, showing a measurable reduction in turn-on dv/dt compared with the baseline case without feedback amplification.

Figure 6.

Simulated waveforms of the resultant currents generated by the proposed AGD at different V_CC voltages. AGD, active gate driver.

Figure 7.

Comparison between simulated waveforms of the gate currents at different operating conditions.

Figure 8.

Simulated V_DS waveforms of the low-side GaN half-bridge under different operating conditions. GaN, gallium nitride.

Compared with Sun et al. (2016), where large capacitors and high bus voltages were required to obtain sufficient gain, this paper demonstrates effective dv/dt regulation using a 0.1 pF sensing capacitor at only 24 V, reducing parasitics and circuit complexity.

Overall, these results demonstrate that the proposed SyncFET–AGD not only validates the necessity of SyncFET-assisted sensing but also achieves MHz-class dv/dt control with a compact, scalable design suitable for GaN converters in the 10 MHz range.

Turn-on switching loss (P_{ON_loss}) in simulation was estimated using the analytical expression (Lidow et al., 2019), as shown in Eq. (8): (8) PONloss=PVt+PCt=12⋅VBUS⋅iL⋅tVF+tCR⋅fSW {P_{{\rm{O}}{{\rm{N}}_{{\rm{loss}}}}}} = {P_{Vt}} + {P_{Ct}} = {1 \over 2} \cdot {V_{{\rm{BUS}}}} \cdot {i_L} \cdot \left( {{t_{{\rm{VF}}}} + {t_{{\rm{CR}}}}} \right) \cdot {f_{{\rm{SW}}}} where V_BUS is the bus voltage, i_L is the load current, t_VF is the drain–source voltage fall time, t_CR is the drain current rise time, and f_SW is the switching frequency. This relation captures the energy dissipated during the overlap of voltage and current in the switching transition, making it a standard approach for estimating GaN switching losses. Experimental measurements were not used for direct loss calculation due to bandwidth limitations of current probes; instead, measured waveforms were employed to validate the simulated switching trends. Table 2 shows a 16.7% reduction in P_{ON_loss} compared with the traditional gate resistance (R_G)-based method, while achieving better dv/dt regulation.

The performance of the proposed SyncFET dv/dt sensor and AGD was validated in a 24 V, 10 MHz buck converter circuit. The experimental validation was carried out on a PCB incorporating the buck converter test circuit. As shown in Figure 9, the PCB layout illustrates the integration of the proposed SyncFET-based dv/dt sensor and the AGD. Figure 10 shows the V_GS waveform of the low-side GaN half-bridge device operating at 4.5 V and 10 MHz. Oscillations were effectively suppressed to <6 V by employing a 7 Ω gate resistance, demonstrating the effectiveness of the design in minimising unwanted transients. As shown in Figure 11, a V_DS voltage overshoot of approximately 43 V is observed during the turn-off transient, despite a nominal input of 24 V. This occurs due to parasitic inductance in the layout and the abrupt interruption of current during turn-off. The effect is more pronounced during turn-off than turn-on, as the rapid decrease in current causes voltage ringing across parasitic elements in the power loop.

Figure 9.

DC–DC buck converter test PCB (photograph). GaN, gallium nitride.

Figure 10.

Measured V_GS waveform of the low-side GaN half-bridge at 4.5 V and 10 MHz. GaN, gallium nitride.

Figure 11.

Measured VDS waveform of the low-side GaN half-bridge during turn-off at 10 MHz. GaN, gallium nitride.

Figures 12 and 13 present experimental V_DS waveforms of the low-side GaN transistor under conditions with and without the proposed SyncFET-based dv/dt sensor and AGD. The results confirm that incorporating the control circuitry substantially moderates the switching transition. As shown in Figure 14, the proposed scheme lowers the dv/dt from 15 V/ns to 10 V/ns, demonstrating effective suppression of excessive switching speed. This improvement, achieved with sub-nanosecond responsiveness at a 10 MHz operating frequency, highlights the capability of the system to enhance switching stability, reliability and may potentially mitigate EMI-related issues in high-frequency GaN converters.

Figure 12.

Measured V_DS waveform of the low-side GaN half-bridge during turn-on without dv/dt control. GaN, gallium nitride.

Figure 13.

Measured V_DS waveform of the low-side GaN half-bridge during turn-on with the proposed dv/dt control. GaN, gallium nitride.

Figure 14.

Comparison of measured V_DS waveforms of the low-side GaN device during turn-on with and without the proposed dv/dt control. GaN, gallium nitride.

It is noted that the oscilloscope used (350 MHz bandwidth, 1.25 GS/s sampling rate) corresponds to a rise/fall-time resolution limit of approximately 1 ns. The measured fall-times of the GaN device range from 1.20 ns to 1.84 ns, which approach this resolution limit. This implies a relative timing uncertainty of about 55%–83% for the fastest transitions. As highlighted in efficient power conversion (EPC) application notes (Biswas et al., 2017), such bandwidth limitations affect the accuracy of absolute fall-time values but do not compromise the validity of relative comparisons, provided the same measurement setup is consistently used. Therefore, while the exact fall-time numbers may carry some error, the observed dv/dt reduction from 15 V/ns to 10 V/ns remains a reliable indicator of the proposed circuit’s effectiveness in moderating switching speed.