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Performance Estimation of Low Power and Area-Efficient Parallel Pipelined FFT Cover

Performance Estimation of Low Power and Area-Efficient Parallel Pipelined FFT

Measurement Science Review
Volume 25 (2025): Issue 3 (June 2025)
By: P Surya,  C Arunachalaperumal and  S Dhilipkumar  
Open Access
|Jun 2025

Authors

P Surya

suryame3020@gmail.com

Anna University, Chennai, India

C Arunachalaperumal

arunachalaperumal@ritrjpm.ac.in

Department of Electronics and Communication Engineering, Ramco Institute of Technology, Rajapalayam, India

S Dhilipkumar

dhilipkumar.s@licet.ac.in

Department of Electronics and Communication Engineering, Loyola ICAM College of Engineering and Technology (LICET), Chennai, India
DOI: https://doi.org/10.2478/msr-2025-0016 | Journal eISSN: 1335-8871
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Language: English
Page range: 134 - 140
Submitted on: Mar 18, 2024
|
Accepted on: May 7, 2025
|
Published on: Jun 17, 2025
Published by: Slovak Academy of Sciences, Institute of Measurement Science
In partnership with: Paradigm Publishing Services
Publication frequency: Volume open
Keywords:
low power fast Fourier transform,
Vedic multiplier,
bit inversion technique,
look-up table,
field programmable gate array,
5G application
Related subjects:
Engineering,
Electrical engineering,
Control engineering, metrology and testing

© 2025 P Surya, C Arunachalaperumal, S Dhilipkumar, published by Slovak Academy of Sciences, Institute of Measurement Science
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.

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