Fig. 1.
Fig. 2.
Fig. 3.
Fig. 4.
Fig. 5.
Fig. 6.
Fig. 7.
j_msr-2025-0016_tab_008
| A = 101 – 1 > 0 = 010, | ||
| B = 111 – 1 > 0 = 000 | ||
| S0 = a0b0 | => 0 × 0 = 1 | (CS = 0) |
| C1S1 = a0b1 + a1b0 | => 0 × 0 + 1 × 0 = 01 | (CS = 1) |
| C2S2 = 0 + a1b1 + a0b2 + a2b0 | => 1 + 1 × 0 + 0 × 0 + 0 × 0 = 01 | (CS = 1) |
| C3S3 = 0 + a1b2 + a2b1 | => 1 + 1 × 0 + 0 × 0 = 01 | (CS = 1) |
| C4S4 = C3 + a2b2 | => 0 + 0 × 0 = 0 | (CS = 0) |
| Total computational cost = 0+1+1+1+0 = 3 | ||
Performance analysis of the proposed BIM-FFT_
| Family | Registers | LUT’s | Slices |
|---|---|---|---|
| Spartan-6 - xc6slx9 | 1179/11440 | 1126/5720 | 475/1430 |
| Virtex-4 - xc4vsx55 | 1246/49152 | 1618/49152 | 1187/24576 |
| Virtex-5 - xc5vsx50t | 1239/32640 | 1548/32640 | 710/8160 |
| Virtex-6 - xc6vlx75t | 106/93129 | 266/46560 | 95/11640 |
| Zynq - xc7z010 | 106/35200 | 265/17,600 | 85/4400 |
j_msr-2025-0016_tab_006
| A=a2a1a0, |
| B=b2b1b0 |
| S0 = a0b0 |
| C1S1 = a0b1 + a1b0 |
| C2S2 = C1 + a1b1 + a0b2 + a2b0 |
| C3S3 = C2 + a1b2 + a2b1 |
| C4S4 = C3 + a2b2 |
Performance analysis of the proposed DPR-FFT architecture with frequency and delay_
| Family | Frequency [MHz] | Delay [ns] | Power [mW] |
|---|---|---|---|
| Spartan-6 - xc6slx9 | 335.768 | 2.97 | 64.15 |
| Virtex-4 - xc4vsx55 | 190.81 | 5.241 | 76.49 |
| Virtex-5 - xc5vsx50t | 188.79 | 5.297 | 75.38 |
| Virtex-6 - xc6vlx75t | 246.77 | 4.052 | 79.01 |
| Zynq - xc7z010 | 261.55 | 3.823 | 64.23 |
j_msr-2025-0016_tab_007
| Let | ||
| A = 101, | ||
| B = 111 | ||
| S0 = a0b0 | => 1 × 1 = 1 | (CS = 1) |
| C1S1 = a0b1 + a1b0 | => 1 × 1 + 1 × 1 = 10 | (CS = 2) |
| C2S2 = C1 + a1b1 + a0b2 + a2b0 | => 1 + 0 × 1 + 1 × 1 + 1 × 1 = 11 | (CS = 3) |
| C3S3 = C2 + a1b2 + a2b1 | => 1 + 0 × 1 + 1 × 1 = 10 | (CS = 2) |
| C4S4 = C3 + a2b2 | => 0 + 1×1 = 01 | (CS = 1) |
| where CS – computational cost | ||
| Total computational cost = 1+2+3+2+1 = 9 | ||
Performance comparison for FFT_
| Device | Methodology | LUTs | Flip-flops | Slices | Frequency [MHz] | Delay [ns] | Power [mW] |
|---|---|---|---|---|---|---|---|
| ASAP 7 nm | R2MDC | 12686 | 7416 | 4005 | 105.234 | 2.835 | 128 |
| Proposed | 9548 | 7239 | 3634 | 188.790 | 1.914 | 75.38 |
Different inversion schemes_
| Input Pattern | Inversion scheme | Output Pattern |
|---|---|---|
| 11111110 | ‘1’s – 7 / ‘0’s – 1 (1>0) Full inversion | 00000001 |
| 10101001 | ‘1’s – 4 / ‘0’s – 4 (1=0) Odd inversion | 00000011 |
| 01010110 | ‘1’s – 4 / ‘0’s – 4 (1=0) Even inversion | 00000011 |
| 00000001 | ‘1’s – 1 / ‘0’s – 7 (0>1) No inversion | 00000001 |
High speed multipliers comparison_
| Multiplier | Power [mW] | Area (LUT) | Delay [ns] | FFT suitability | Utilization |
|---|---|---|---|---|---|
| Booth | 2.35 | 150 | 12.5 | Moderate | Moderate area and speed |
| Wallace tree | 2.10 | 180 | 10.3 | High | High-speed, but complex logic increases area |
| Dadda | 2.25 | 160 | 9.8 | High | Similar to Wallace |
| Baugh-Wooley | 2.40 | 170 | 11.0 | Moderate | Best for 2’s complement |
| Approximate LOA | 1.50 | 120 | 8.5 | Medium | Power-efficient, may introduce slight computational error |