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Pt/Al2O3/HfO2/Ti/TiN bi-layer RRAM device for imply–inhibit logic applications: Unveiling the resistive potential by experiment and simulation Cover

Pt/Al2O3/HfO2/Ti/TiN bi-layer RRAM device for imply–inhibit logic applications: Unveiling the resistive potential by experiment and simulation

Open Access
|Mar 2025

Figures & Tables

Figure 1

Step-by-step process of fabricating the proposed RRAM device.
Step-by-step process of fabricating the proposed RRAM device.

Figure 2

Proposed 1T-1R structure for imply–inhibit logic gates.
Proposed 1T-1R structure for imply–inhibit logic gates.

Figure 3

(a) Cross-sectional HRTEM image of the Pt/Al2O3/HfO2/Ti/TiNbi-layer RRAM structure. (b) The closer view of layer deposition and its interface.
(a) Cross-sectional HRTEM image of the Pt/Al2O3/HfO2/Ti/TiNbi-layer RRAM structure. (b) The closer view of layer deposition and its interface.

Figure 4

XRD pattern of Al2O3 and HfO2 nanoparticles.
XRD pattern of Al2O3 and HfO2 nanoparticles.

Figure 5

XPS spectra of the Al2O3/HfO2 bi-layer structure. (a) Al2p, (b) Hf4f peaks, (c) O 1-s peak of the Al2O3 layer, and (d) O 1-s peak of the HfO2 layer.
XPS spectra of the Al2O3/HfO2 bi-layer structure. (a) Al2p, (b) Hf4f peaks, (c) O 1-s peak of the Al2O3 layer, and (d) O 1-s peak of the HfO2 layer.

Figure 6

Resistive switching characteristics of the device unit and distribution of the SET and RESET voltages. (a) Typical resistive switching characteristics of the device, (b) durability of the device unit, (c) memory retention of HRS and LRS for 103 s with a read voltage of 0.2 V, and (d) resistive switching mechanism of the Pt/Al2O3/HfO2/Ti/TiN RRAM during the SET and RESET process.
Resistive switching characteristics of the device unit and distribution of the SET and RESET voltages. (a) Typical resistive switching characteristics of the device, (b) durability of the device unit, (c) memory retention of HRS and LRS for 103 s with a read voltage of 0.2 V, and (d) resistive switching mechanism of the Pt/Al2O3/HfO2/Ti/TiN RRAM during the SET and RESET process.

Figure 7

Resistive switching characteristics of the Pt/Al2O3/HfO2/TiN device. (a) Typical I–V characteristics of the device, (b) forming behavior, (c) durability of the device, and (d) memory retention of HRS and LRS for 103 s with a read voltage of 0.2 V.
Resistive switching characteristics of the Pt/Al2O3/HfO2/TiN device. (a) Typical I–V characteristics of the device, (b) forming behavior, (c) durability of the device, and (d) memory retention of HRS and LRS for 103 s with a read voltage of 0.2 V.

Figure 8

(a) Cycle-to-cycle variation in I–V characteristics of Pt/Al2O3/HfO2/TiN device, (b) cycle-to-cycle variation in I–V characteristics of the Pt/Al2O3/HfO2/Ti/TiN device, (c) and (d) SET and RESET voltage distribution of the Pt/Al2O3/HfO2/TiN device, and (e) and (f) SET and RESET voltage distribution of the Pt/Al2O3/HfO2/Ti/TiN device.
(a) Cycle-to-cycle variation in I–V characteristics of Pt/Al2O3/HfO2/TiN device, (b) cycle-to-cycle variation in I–V characteristics of the Pt/Al2O3/HfO2/Ti/TiN device, (c) and (d) SET and RESET voltage distribution of the Pt/Al2O3/HfO2/TiN device, and (e) and (f) SET and RESET voltage distribution of the Pt/Al2O3/HfO2/Ti/TiN device.

Figure 9

The circuit diagram for a 1-bit adder with a combination of inhibit, imply, and XNOR logic gates.
The circuit diagram for a 1-bit adder with a combination of inhibit, imply, and XNOR logic gates.

Figure 10

(a) Hysteresis curve of the simulation results superimposed on the experimental results, (b) simulated waveform of imply logic, (c) simulated waveform of inhibit logic, (d) simulated waveform of XNOR logic, (e) simulated waveform of half-adder, and (f) simulated waveform of full-adder.
(a) Hysteresis curve of the simulation results superimposed on the experimental results, (b) simulated waveform of imply logic, (c) simulated waveform of inhibit logic, (d) simulated waveform of XNOR logic, (e) simulated waveform of half-adder, and (f) simulated waveform of full-adder.

Figure 11

PDP and transistor count comparison between proposed logic style and CMOS logic style.
PDP and transistor count comparison between proposed logic style and CMOS logic style.

Truth table for simulated logic gates_

InputsLogic gates
A B NOTANDORIMPLYINHIBITNANDNORXORXNOR
00100011101
01101111010
10001001010
11011010001

Comparison between proposed memristor-based logic circuits and other logic circuits_

FunctionLogic circuitsComponentPower (µW)Delay (ps)
XOR1T2M-based logic [19]1T + 6R15648.7
Universal logic [20]2T + 2R + 1 resistor25.7716.74
MeMOS logic [21]4T + 6R2.0830.6
CMOS logic [22]8T + 2 inverter28.4287.5 × 103
Proposed logic4T + 4R1.95525.6
XNOR1T2M-based logic1T + 6R16851.7
Universal logic2T + 2R + 1 resistor36.28
MeMOS logic4T + 6R2.4131.11
Proposed logic3T + 3R1.18223.68
NOT1T2M-based logic1T + 2R14245.03
MeMOS logic2T0.518.7
CMOS logic2T0.08613.04
Proposed logic1T + 1R0.9167.262
Half-adderMeMOS logic8T + 8R8.0798.05
Proposed logic6T + 6R1.99642.5
1-bit Adder1T2M-based logic3T + 16R30757.93
Universal logic16T + 10R + 2 resistor13469.3
MeMOS logic16T + 18R17.87212.3
Proposed logic7T + 7R2.77574.2
IMPLYCMOS logic6T0.21838.91
Proposed logic1T + 1R0.4637.221
INHIBITCMOS logic6T0.22842.38
Proposed logic1T + 1R0.4513.49
DOI: https://doi.org/10.2478/msp-2025-0016 | Journal eISSN: 2083-134X | Journal ISSN: 2083-1331
Language: English
Page range: 196 - 209
Submitted on: Feb 5, 2025
Accepted on: May 25, 2025
Published on: Mar 31, 2025
Published by: Wroclaw University of Science and Technology
In partnership with: Paradigm Publishing Services
Publication frequency: 4 issues per year

© 2025 Nithya Natarajan, Paramasivam Kuppusamy, published by Wroclaw University of Science and Technology
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.