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High-level area estimation model for FPGA-based designs using LLVM

International Journal on Smart Sensing and Intelligent Systems
Volume 18 (2025): Issue 1 (January 2025)
By:
Open Access
|Aug 2025

Figures & Tables

Figure 1:

Research methodology flowchart.
Research methodology flowchart.

Figure 2:

Regression Analyses of Operational Units.
Regression Analyses of Operational Units.

Figure 3:

Area estimation error comparison chart.
Area estimation error comparison chart.

Coefficients for LUT estimation models for Virtex-5(XC5VLX50)

Operational Unit P0K {\bf{P}}_{\bf{0}}^{\bf{K}} P1K {\bf{P}}_{\bf{1}}^{\bf{K}} P2K {\bf{P}}_{\bf{2}}^{\bf{K}} P3K {\bf{P}}_{\bf{3}}^{\bf{K}} P4K {\bf{P}}_{\bf{4}}^{\bf{K}} P5K {\bf{P}}_{\bf{5}}^{\bf{K}}
Bitwise logical operation−0.30620.5759−1.329×10−4–––
Adder/Subtractor02––––
Shift register0.95870.02605−0.0041922.039×10−4−2.081×10−6–
Multiplexer1.1220.16090.04224−1.231×10−31.061×10−5–
Comparator4.33−0.8480.2229−6.81×10−35.978×10−5–
Multiplier0.86981.133−0.28990.01588−1.454×10−4–

Coefficients for LUT estimation models for Virtex-2pro(XC2VP2)

Operational Unit P0K {\bf{P}}_{\bf{0}}^{\bf{K}} P1K {\bf{P}}_{\bf{1}}^{\bf{K}} P2K {\bf{P}}_{\bf{2}}^{\bf{K}} P3K {\bf{P}}_{\bf{3}}^{\bf{K}} P4K {\bf{P}}_{\bf{4}}^{\bf{K}} P5K {\bf{P}}_{\bf{5}}^{\bf{K}}
Bitwise logical operation01––––
Adder/Subtractor0.12920.96949.309×10−4–––
Shift register01––––
Multiplexer−0.30620.5759−1.329×10−4–––
Comparator−5.8864.484−0.14810.004−3.345×10−5–
Multiplier0.86981.133−0.28990.01588−1.454×10−4–

Coefficients for LUT estimation models for Spartan 3E(XC3S500E)

Operational Unit P0K {\bf{P}}_{\bf{0}}^{\bf{K}} P1K {\bf{P}}_{\bf{1}}^{\bf{K}} P2K {\bf{P}}_{\bf{2}}^{\bf{K}} P3K {\bf{P}}_{\bf{3}}^{\bf{K}} P4K {\bf{P}}_{\bf{4}}^{\bf{K}} P5K {\bf{P}}_{\bf{5}}^{\bf{K}}
Bitwise logical operation00.5––––
Adder/Subtractor0.12920.96949.309×10−4–––
Shift register01––––
Multiplexer−0.30620.5759−1.329×10−4–––
Comparator−5.8864.484−0.14810.004−3.345×10−5–
Multiplier5.676−3.1610.704−0.022154.935×10−4−3.76×10−6

Operational Unit Assignment

Number(k)Operational Unit
1Bitwise logical operation
2Adder/Subtractor
3Shift register
4Multiplexer
5Comparator
6Multiplier

Coefficients for Flip-flop estimation models for Target Device

Target Device(f) P1f {\bf{P}}_{\bf{1}}^{\bf{f}} P2f {\bf{P}}_{\bf{2}}^{\bf{f}} P3f {\bf{P}}_{\bf{3}}^{\bf{f}} P4f {\bf{P}}_{\bf{4}}^{\bf{f}} P5f {\bf{P}}_{\bf{5}}^{\bf{f}}
Spartan 3E(1)0.76670.8726000
Virtex-2pro(2)−0.39180.6792000
Virtex-5(3)0.87670.02006−8.2×10−41.965×10−5−1.32×10−7
DOI: https://doi.org/10.2478/ijssis-2025-0042 | Journal eISSN: 1178-5608
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Language: English
Submitted on: Oct 11, 2024
Published on: Aug 8, 2025
Published by: Professor Subhas Chandra Mukhopadhyay
In partnership with: Paradigm Publishing Services
Publication frequency: 1 issue per year
Keywords:
FPGA,
High-level synthesis,
Design Space Exploration,
Low-Level Virtual Machine
Related subjects:
Engineering,
Introductions and overviews,
Engineering, other

© 2025 Rachna Singh, Gunjan Gupta, published by Professor Subhas Chandra Mukhopadhyay
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.

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