High-level area estimation model for FPGA-based designs using LLVM

Rachna Singh; Gunjan Gupta

doi:10.2478/ijssis-2025-0042

.blurhash-client-img { display: none !important; }

High-level area estimation model for FPGA-based designs using LLVM

International Journal on Smart Sensing and Intelligent Systems

Volume 18 (2025): Issue 1 (January 2025)

By: Rachna Singh and Gunjan Gupta

Open Access

|Aug 2025

Figures & Tables

Regression Analyses of Operational Units.

Table 1:

Operational Unit Assignment

Number(k)	Operational Unit
1	Bitwise logical operation
2	Adder/Subtractor
3	Shift register
4	Multiplexer
5	Comparator
6	Multiplier

Table 2:

Coefficients for LUT estimation models for Spartan 3E(XC3S500E)

Operational Unit	$P_{0}^{K}$	$P_{1}^{K}$	$P_{2}^{K}$	$P_{3}^{K}$	$P_{4}^{K}$	$P_{5}^{K}$
Bitwise logical operation	0	0.5	–	–	–	–
Adder/Subtractor	0.1292	0.9694	9.309×10⁻⁴	–	–	–
Shift register	0	1	–	–	–	–
Multiplexer	−0.3062	0.5759	−1.329×10⁻⁴	–	–	–
Comparator	−5.886	4.484	−0.1481	0.004	−3.345×10⁻⁵	–
Multiplier	5.676	−3.161	0.704	−0.02215	4.935×10⁻⁴	−3.76×10⁻⁶

Table 3:

Coefficients for LUT estimation models for Virtex-2pro(XC2VP2)

Operational Unit	$P_{0}^{K}$	$P_{1}^{K}$	$P_{2}^{K}$	$P_{3}^{K}$	$P_{4}^{K}$	$P_{5}^{K}$
Bitwise logical operation	0	1	–	–	–	–
Adder/Subtractor	0.1292	0.9694	9.309×10⁻⁴	–	–	–
Shift register	0	1	–	–	–	–
Multiplexer	−0.3062	0.5759	−1.329×10⁻⁴	–	–	–
Comparator	−5.886	4.484	−0.1481	0.004	−3.345×10⁻⁵	–
Multiplier	0.8698	1.133	−0.2899	0.01588	−1.454×10⁻⁴	–

Table 4:

Coefficients for LUT estimation models for Virtex-5(XC5VLX50)

Operational Unit	$P_{0}^{K}$	$P_{1}^{K}$	$P_{2}^{K}$	$P_{3}^{K}$	$P_{4}^{K}$	$P_{5}^{K}$
Bitwise logical operation	−0.3062	0.5759	−1.329×10⁻⁴	–	–	–
Adder/Subtractor	0	2	–	–	–	–
Shift register	0.9587	0.02605	−0.004192	2.039×10⁻⁴	−2.081×10⁻⁶	–
Multiplexer	1.122	0.1609	0.04224	−1.231×10⁻³	1.061×10⁻⁵	–
Comparator	4.33	−0.848	0.2229	−6.81×10⁻³	5.978×10⁻⁵	–
Multiplier	0.8698	1.133	−0.2899	0.01588	−1.454×10⁻⁴	–

Table 5:

Coefficients for Flip-flop estimation models for Target Device

Target Device(f)	$P_{1}^{f}$	$P_{2}^{f}$	$P_{3}^{f}$	$P_{4}^{f}$	$P_{5}^{f}$
Spartan 3E(1)	0.7667	0.8726	0	0	0
Virtex-2pro(2)	−0.3918	0.6792	0	0	0
Virtex-5(3)	0.8767	0.02006	−8.2×10⁻⁴	1.965×10⁻⁵	−1.32×10⁻⁷

References

Authors

Metrics

Articles in this issue

DOI: https://doi.org/10.2478/ijssis-2025-0042 | Journal eISSN: 1178-5608

Journal RSS Feed

Language: English

Submitted on: Oct 11, 2024

Published on: Aug 8, 2025

Published by: International Journal on Smart Sensing and Intelligent Systems

In partnership with: Paradigm Publishing Services

Publication frequency: Volume open

Keywords:

FPGA,

High-level synthesis,

Design Space Exploration,

Low-Level Virtual Machine

Related subjects:

Engineering,

Introductions and overviews,

Engineering, other

© 2025 Rachna Singh, Gunjan Gupta, published by International Journal on Smart Sensing and Intelligent Systems
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.

Volume 18 (2025): Issue 1 (January 2025)

High-level area estimation model for FPGA-based designs using LLVM

Figures & Tables

Figure 1:

Figure 2:

Table 1:

Table 2:

Table 3:

Table 4:

Table 5:

Figure 3:

Paradigm

My account