High-level area estimation model for FPGA-based designs using LLVM

The functional segregation of a system into interacting hardware and software components needs estimation of the hardware area at an early design space exploration. However, the early estimation of design parameters from high-level programs is a time-consuming process, so a model is required for faster estimation of these parameters. This study presents a mathematical model for fast and accurate estimation of hardware area for implementations using the FPGAs family. In this study, a mathematical model is presented, which estimates the maximum number of LUTs and flip-flops consumed by different FPGAs. The input to this mathematical model is a high-level description in C language. The hardware synthesis of different FPGAs is done by using a low-level virtual machine (LLVM). The FPGAs used for the above work are Spartan 3E, Virtex-2pro, and Virtex-5, for which accuracy and run time for each model were determined. The results show that the estimation error for LUT is in the range of 1.11%–2.5% for Spartan 3E, 0.94%–2.4% for Virtex-2pro, and 1.32%–2.75% for Virtex-5. Similarly, the estimation error for flip-flops is in the range of 2.9%–4.9% for Spartan 3E, 3.2%–5.0% for Virtex-2pro, and 3.5%–5.2% for Virtex-5.