High-level area estimation model for FPGA-based designs using LLVM
By:
Authors
Rachna Singh
Department of Electronics & Communication Engineering, JIIT, Noida, India
DOI: https://doi.org/10.2478/ijssis-2025-0042 | Journal eISSN: 1178-5608
Language: English
Submitted on: Oct 11, 2024
Published on: Aug 8, 2025
Published by: Professor Subhas Chandra Mukhopadhyay
In partnership with: Paradigm Publishing Services
Publication frequency: 1 issue per year
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© 2025 Rachna Singh, Gunjan Gupta, published by Professor Subhas Chandra Mukhopadhyay
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.