Have a personal or library account? Click to login
High-level area estimation model for FPGA-based designs using LLVM Cover

High-level area estimation model for FPGA-based designs using LLVM

International Journal on Smart Sensing and Intelligent Systems
Volume 18 (2025): Issue 1 (January 2025)
By: Rachna Singh and  Gunjan Gupta  
Open Access
|Aug 2025

Authors

Rachna Singh

rachna.singh@mail.jiit.ac.in

Department of Electronics & Communication Engineering, JIIT, Noida, India

Gunjan Gupta

guptag@cput.ac.za

Cape Peninsula University of Technology, Bellville, South Africa
DOI: https://doi.org/10.2478/ijssis-2025-0042 | Journal eISSN: 1178-5608
Journal RSS Feed
Language: English
Submitted on: Oct 11, 2024
|
Published on: Aug 8, 2025
Published by: Professor Subhas Chandra Mukhopadhyay
In partnership with: Paradigm Publishing Services
Publication frequency: 1 issue per year
Keywords:
FPGA,
High-level synthesis,
Design Space Exploration,
Low-Level Virtual Machine
Related subjects:
Engineering,
Introductions and overviews,
Engineering, other

© 2025 Rachna Singh, Gunjan Gupta, published by Professor Subhas Chandra Mukhopadhyay
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.

Previous articleVolume 18 (2025): Issue 1 (January 2025)Next article