Have a personal or library account? Click to login
A study on the design of D flip-flop with set and reset using GDI scheme Cover

A study on the design of D flip-flop with set and reset using GDI scheme

Open Access
|Jul 2025

Figures & Tables

Figure 1:

Basic GDI cell and its function. GDI, gate diffusion input.
Basic GDI cell and its function. GDI, gate diffusion input.

Figure 2:

Functional block diagram of fingerprint sensor chip. (A) AND (B) OR (C) MUX.
Functional block diagram of fingerprint sensor chip. (A) AND (B) OR (C) MUX.

Figure 3:

Hybrid GDI technique. GDI, gate diffusion input.
Hybrid GDI technique. GDI, gate diffusion input.

Figure 4:

Conventional CMOS set/reset D flip-flop (DFFSR_C).
Conventional CMOS set/reset D flip-flop (DFFSR_C).

Figure 5:

Proposed GDI set/reset D flip-flop (DFFSR_G). CK, DFFSR_G, GDI, gate diffusion input.
Proposed GDI set/reset D flip-flop (DFFSR_G). CK, DFFSR_G, GDI, gate diffusion input.

Figure 6:

Functional simulation result of DFFSR_G.
Functional simulation result of DFFSR_G.

Figure 7:

Verilog-HDL based RTL code for synthesis and P&R verification using DFFSR_G. P&R, placement and routing.
Verilog-HDL based RTL code for synthesis and P&R verification using DFFSR_G. P&R, placement and routing.

Figure 8:

Configuration condition for openROAD.
Configuration condition for openROAD.

Figure 9:

SDC condition for openROAD.
SDC condition for openROAD.

Figure 10:

Layout result of 64 bit counter using DFFSR_G.
Layout result of 64 bit counter using DFFSR_G.

Functions of GDI technique_

Input
OutputFunction
GPN
AB‘1’A + BOR
A‘0’BA·BAND
ABC A¯B+AC {\rm{\bar A}}{\rm{B}}+{\rm{AC}} MUX
A‘1’‘0’ A¯ {\rm{\bar A}} NOT

Truth table of DFFSR operation_

RNSNDCKQ[n+1]QN[n+1]
00XX01
10XX10
00XX10
11001
11110
11XQ[n]QN[n]

Summary of 64 bit counter P&R_

DFFSR_CDFFSR_G
Number of I/O ports131
Number of nets390
Number of cells196

Combinational area (µm2)4301.04301.0
Noncombinational area (µm2)5535.14317.4
Total cell area (µm2)9836.28618.4

Summary of DFFSR performance comparison_

Number of MOS TR.clk_q_tplh (sec)clk_q_tphl (sec)average (sec)power_avg (uW/MHz)
DFFSR_C423.60E-103.17E-103.39E-100.211
DFFSR_G285.97E-106.04E-106.00E-100.205
Improvement33% –77%3%
Language: English
Submitted on: May 6, 2025
Published on: Jul 18, 2025
Published by: Professor Subhas Chandra Mukhopadhyay
In partnership with: Paradigm Publishing Services
Publication frequency: 1 times per year

© 2025 Seungmin Jung, published by Professor Subhas Chandra Mukhopadhyay
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.