A study on the design of D flip-flop with set and reset using GDI scheme

In this study, we propose a new D flip-flop (DFF) logic gate that includes a set/reset function using gate diffusion input (GDI) technology. Since this cell can be implemented with about 33% less MOS transistors than a conventional CMOS set/reset DFF, it is expected to significantly reduce the chip area occupied by sequential circuits. The cell characteristics were extracted using HSPICE, and a library for Synopsys DC, a synthesis tool, was developed. To verify the applicability of the RTL design flow, a 64-bit counter was designed, logic circuit synthesis was performed, and placement and routing (P&R) layout was performed using openROAD tool. The designed 64-bit counter showed a 22% increase in area in the sequential circuit.