Impact of lanthanum doped zirconium oxide (LaZrO2) gate dielectric material on FinFET inverter
References
- Ana, F. and Din, N. U. 2011. Gate workfunction engineering for deep sub-micron MOSFET’s: motivation, features and challenges. International Journal of Electronics and Communication Technology 2: 29–35.
- Aujla, S. K. and Kaur, N. 2019. Optimization of dual-K gate dielectric and dual gate heterojunction SOI FinFET at 14 nm gate length. IETE Journal of Research 1–9.
- Bortolon, F. T. 2018. Static Noise Margin Analysis for CMOS Logic Cells in Near-Threshold. Master dissertation, Universidade Federal Do Rio Grande Do Sul, Brazil.
- Businesswire 2017. available at: https://www.businesswire.com/news/home/20170607005803/en/Global-FinFET-Technology-Market-2017-2021-With-Intel TSMC-Samsung-GlobalFoundries-SMIC-Qualcomm-Dominating-Research-and-Markets.
- Chakraborty, A. S., Chanda, M. and Sarkar, C. K. 2013. “Analysis of noise margin of CMOS inverter in sub-threshold regime”, 2013 Students Conference on Engineering and Systems (SCES), Allahabad, April 12-14.
- Chen, F., Bin, X., Hella, C., Shi, X., Gladfelter, W. L. and Campbell, S. A. 2004. A study of mixtures of HfO2 and TiO2 as high-k gate dielectrics. Microelectronics Engineering 72: 263–266.
- Cheng, B., Cao, M., Rao, R., Inani, A., Voorde, P. V., Greene, W. M., Stork, J. M., Yu, Z., Zeitzoff, P. M. and Woo, J. C. 1999. The impact of high-gate dielectrics and metal gate electrodes on sub-100 nm MOSFET’s. IEEE Transactions on Electron Devices 46(7): 1537–1544.
- Colinge, J. P. 2008. Handbook of FinFETs and other Multi-gate Transistors Springer Science+ Business Media Publishers, Springer-Verlag US.
- de Andrade, M. G. C., Martino, J. A., Aoulaiche, M., Collaert, N., Simoen, E. and Claeys, C. 2011. “Behavior of triple-gate bulk FinFETs with and without DTMOS operation”, Proceedings of the IEEE International Conference on Ultimate Integration of Silicon, Cork, Ireland, March 14-16.
- Eng, Y. C., Hu, L., Chang, T. F., Hsu, S., Chiou, C. M., Wang, T., Yang, C. W., Cheng, O., Wang, C. Y., Tseng, C. S. and Huang, R. 2018. Importance of VDIBLSS/(Ion/Ioff) in evaluating the performance of N-channel bulk FinFET devices. IEEE Journal of Electron Devices Society 6: 207–213.
- Gargini, P. 2020. ITRS past, present and future. ITRS 2.0 publication, 2015. available at: http://www.itrs2.net/itrs-reports.html/ (accessed July 2020).
- Gaskell, J. M., Jones, A. C., Aspinall, H. C., Taylor, S., Taechakumput, P., Chalker, P. R., Heys, P. N. and Odedra, R. C. 2007. Deposition of lanthanum zirconium oxide high-κ films by liquid injection atomic layer deposition. Applied Physics Letter 91(11): 112912.
- Karbalaei, M., Dideban, D. and Heidari, H. 2020. Impact of high-k gate dielectric with different angles of coverage on the electrical characteristics of gate-all-around field effect transistor: a simulation study. Results in Physics 16: 1–17.
- Kaur, A., Mehra, R. and Saini, A. 2019. Hetero-dielectric oxide engineering on dopingless gate all around nanowire MOSFET with Schottky contact source/drain. AEU – International Journal of Electronics and Communications 111: 1–8.
- Kaur, G., Gill, S. S. and Rattan, M. 2020a. Whale optimization algorithm for performance improvement of silicon-on-insulator FinFETs. International Journal of Artificial Intelligence 18(1): 63–81.
- Kaur, G., Gill, S. S. and Rattan, M. 2020b. Impact of high-k gate dielectric and workfunctions variation on Electrical Characteristics of VeSFET. International Conference on Advanced Machine Learning Technologies and Applications (AMLTA 2020), Jaipur, February.
- Kaur, N., Rattan, M. and Gill, S. S. 2018. Design and optimization of novel shaped FinFET. Arabian Journal of Science and Engineering 44: 3101–3116.
- Knoblinger, G., Fulde, M. and Pacha, C. 2008. “Multi-gate MOSFET circuit design”, In Colinge, J. P. (Ed.), FinFETs and other Multi-gate Transistors, Springer, Boston, MA, pp. 293–335, available at: https://doi.org/10.1007/978-0-387-71752-4_7.
- Lee, J. H. 2016. Bulk FinFETs: design at 14 nm node and key characteristics. Nano Devices and Circuit Techniques for Low-Energy Applications and Energy Harvesting, Dordrecht: KAIST Research Series, Springer Science+Business Media, pp. 33–64.
- Li, Y., Hwang, C. H. and Yu, S. M. 2007. Numerical simulation of static noise margin for a six-transistor static random access memory cell with 32nm fin typed field effect transistor. Computational Science-ICCS 2007, Beijing, May 27-30, Lecture notes in Computer Science 4490, Springer, Berlin, Heidelberg.
- Liu, L. N., Tang, W. M. and Lai, P. T. 2019. Review: advances in La-based high-k dielectrics for MOS applications. Coatings 9(4): 1–30.
- Mohapatra, S. K., Pradhan, K. P., Singh, D. and Sahu, P. K. 2015. The role of geometry parameters and fin aspect ratio of sub-20nm SOI-FinFET: an analysis towards analog and RF circuit design. IEEE Transactions on Nanotechnology 14(3): 546–554.
- Nayak, K., Bajaj, M., Konar, A., Oldiges, P. J., Natori, K., Iwai, H., Murali, K. V. and Rao, V. R. 2014. CMOS logic device and circuit performance of Si gate all around nanowire MOSFET. IEEE Transaction on Electron Devices 61(9): 3066–3074.
- Nirmal, D., Vijayakumar, P., Samuel, P. P. C., Jebalin, B. K. and Mohankumar, N. 2012. Subthreshold analysis of nanoscale FinFETs for ultra-low power application using high-k materials. International Journal of Electronics 10(6): 1–15.
- Pattanaik, M., Birla, S. and Singh, R. K. 2012. Effect of temperature & supply voltage variation on stability of 9T SRAM cell at 45 nm technology for various process corners. Circuits and Systems 3(2): 200–204.
- Pindoo, I. A. and Sinha, S. K. 2020. Increased sensitivity of biosensors using evolutionary algorithm for bio-medical applications. Radioelectronics and Communications Systems 63: 308–318.
- Pradhan, K. P., Mohapatra, S. K., Sahu, P. K. and Behera, D. K. 2014. Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET. Microelectronics Journal 45(2): 144–151.
- Rathee, G., Sharma, A. and Kumar, R. 2019. A secure communicating things network framework for industrial IoT using blockchain Technology. Ad Hoc Network Vol. 94 p. 101933.
- Sachid, A. B. and Chenming, H. 2012. A Little Known Benefit of FinFET over Planar MOSFET in High-Performance Circuits at Advanced Technology Nodes Napa, CA, USA, Proc. IEEE Int. SOI Conf.
- Sathya, N., Anto Bennet, M., Mageswari, M., Priya, M. and Kayalvizhi, M. 2017. Design of low complexity accumulator using FinFET for various technologies. International Journal on Smart Sensing and Intelligent Systems 10(5): 225–235.
- Sharma, A. and Kumar, R. 2019a. A constrained framework for context-aware remote E-healthcare (CARE) services. Transactions on Emerging Telecommunications Technologies e3649, available at: https://doi.org/10.1002/ett.3649.
- Sharma, A. and Kumar, R. 2019b. Service-level agreement—energy cooperative quickest ambulance routing for critical healthcare services. Arabian Journal for Science and Engineering 44: 3831–3848.
- Siebel, O. F., Schneider, M. C. and Galup-Montoro, C. 2012. MOSFET threshold voltage: definition, extraction and some applications. Microelectronics Journal 43(5): 329–336.
- VLSI System Design, VLSI Basics 2019. available at: https://www.vlsisystemdesign.com/noise-margin/Noise margin formula.
- Wikipedia 14nm process 2020. available at: https://en.wikipedia.org/wiki/14_nm_process.
- Genius User Guide. 2009. Singapore: Cogenda, available at: http://www.i vis.co.jp/pdf/cogenda/User_Guide.pdf.
- Yeh, M. S., Luo, G. L., Hou, F. J., Sung, P. J., Wang, C. J., Su, C. J., Wu, C. T., Huang, Y. C., Hong, T. C., Chen, B. Y. and Chen, K. M. 2018. GeFinFET CMOS inverters with improved channel surface roughness by using in-situ ALD digital O3 treatment. Proceedings IEEE 2nd Electron Devices Technology and Manufacturing Conference Proceedings of Technical Papers, Kobe, Japan, July.
- Zhao, C., Zhao, C. Z., Werner, M., Taylor, S. and Chalker, P. R. 2012. Review article: advanced CMOS gate stack: present research progress. International Scholarly Research Nanotechnology Notices 2012: 1–35, available at: https://doi.org/10.5402/2012/689023.
- Zhao, C., Zhao, C. Z., Tao, J., Werner, M., Taylor, S. and Chalker, P. R. 2012. Dielectric relaxation of lanthanide-based ternary oxides: physical and mathematical models. Journal of Nanomaterials 12: 1–6.
- Zhao, C. Z., Werner, M., Taylor, S., Chalker, P. R., Jones, A. C. and Zhao, C. 2011. Dielectric relaxation of La-doped zirconia caused by annealing ambient. Nanoscale Research Letter 6(1): 1–6.
DOI: https://doi.org/10.21307/ijssis-2020-032 | Journal eISSN: 1178-5608
Language: English
Page range: 1 - 10
Submitted on: Sep 19, 2020
Published on: Nov 19, 2020
Published by: Professor Subhas Chandra Mukhopadhyay
In partnership with: Paradigm Publishing Services
Publication frequency: 1 issue per year
Keywords:
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© 2020 Gurpurneet Kaur, Sandeep Singh Gill, Munish Rattan, published by Professor Subhas Chandra Mukhopadhyay
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.