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Loop profiling tool for HPC code inspection as an efficient method of FPGA based acceleration Cover

Loop profiling tool for HPC code inspection as an efficient method of FPGA based acceleration

International Journal of Applied Mathematics and Computer Science
Volume 20 (2010): Issue 3 (September 2010)
By: Marcin Pietroń,  Paweł Russek and  Kazimierz Wiatr  
Open Access
|Sep 2010
DOI: https://doi.org/10.2478/v10006-010-0043-1 | Journal eISSN: 2083-8492 | Journal ISSN: 1641-876X
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Language: English
Page range: 581 - 589
Published on: Sep 27, 2010
Published by: University of Zielona Góra
In partnership with: Paradigm Publishing Services
Publication frequency: 4 issues per year
Keywords:
HPC,
HPRC (High Performance Reconfigurable Computing),
loop profiling,
Mitrion-C,
DFG (Data Flow Graph)
Related subjects:
Mathematics,
Applied mathematics

© 2010 Marcin Pietroń, Paweł Russek, Kazimierz Wiatr, published by University of Zielona Góra
This work is licensed under the Creative Commons License.

Volume 20 (2010): Issue 3 (September 2010)