Loop profiling tool for HPC code inspection as an efficient method of FPGA based acceleration
By: Marcin Pietroń, Paweł Russek and Kazimierz Wiatr
Open Access
|Sep 2010References
- Bennett, D., Dellinger, E., Mason, J. and Sundarajan, P. (2006). An FPGA-oriented target language for HLL compilation,
- Deng, L., Kim, J. S., Mangalagiri, P., Irick, K., Sobti, K., Kandemir, M., Narayanan, V., Chakrabarti, Ch., Pitsianis, N. and Sun, X. (2009). An automated framework for accelerating numerical algorithms on reconfigurable platform using algorithmic/architectural optimization,(12): 1654-1667.
- Gasper, P., Herbst, C., McCough, J., Rickett, C. and Stubbendieck, G. (2003). Automatic parallelization of sequential C code,
- Gong, W., Wang, G. and Kastner, R. (2004). A high performance application representation for reconfigurable systems,
- Kindratenko, V., Brunner, R. and Myers, A. (2007). Mitrion-C application development on SGI Altix 350/RC100,, pp. 239-250.
- Kindratenko, V., Myers, A. and Brunner, R. (2006). Exploring coarse- and fine-grain parallelism on a high-performance reconfigurable computer,
- Liu, K., Cameron, Ch. and Sarkady, A. (2008). Using Mitrion-C to implement floating-point arithmetic on a Cray XD1 supercomputer,, pp. 391-395.
- Memik, S. O., Bozorgzadeh, G., Kastner, R. and Sarrafzadeh, M. (2005). A scheduling algorithm for optimization and planning in high-level synthesis,(1).
- Messmer, P. and Bodenner R. (2006). Accelerating scentific applications using FPGAs,(1): 33-57.
- Mohl, S. (2006). The Mitrion-C programming language, Mitrionics Inc., Second Quarter, pp. 70-73
- Moseley, T., Grunwald, D., Connors, A., Ramanujam, R., Tovinkere, V. and Peri R. (2006). LoopProf: Dynamic techniques for loop detection and profiling,
- Pietroń, M., Wiatr, K. and Russek, P. (2007(a)). Methodology of computing acceleration using reconfigurable logic technology in high performance computing,, pp. 149-156.
- Pietroń, M., Russek, P., Wiatr, K., Jamro, E. and Wielgosz, M. (2007(b)). Two electron integrals calculation accelerated with double precision exp() hardware module,
- Russek, P. and Wiatr, K. (2006). The prospect of computing acceleration using reconfigurable logic technology in huge computational power systems,, pp. 44-49.
Language: English
Page range: 581 - 589
Published on: Sep 27, 2010
Published by: University of Zielona Góra
In partnership with: Paradigm Publishing Services
Publication frequency: 4 issues per year
Keywords:
Related subjects:
© 2010 Marcin Pietroń, Paweł Russek, Kazimierz Wiatr, published by University of Zielona Góra
This work is licensed under the Creative Commons License.