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Loop profiling tool for HPC code inspection as an efficient method of FPGA based acceleration Cover

Loop profiling tool for HPC code inspection as an efficient method of FPGA based acceleration

Open Access
|Sep 2010

References

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DOI: https://doi.org/10.2478/v10006-010-0043-1 | Journal eISSN: 2083-8492 | Journal ISSN: 1641-876X
Language: English
Page range: 581 - 589
Published on: Sep 27, 2010
In partnership with: Paradigm Publishing Services
Publication frequency: 4 issues per year

© 2010 Marcin Pietroń, Paweł Russek, Kazimierz Wiatr, published by University of Zielona Góra
This work is licensed under the Creative Commons License.

Volume 20 (2010): Issue 3 (September 2010)