References
- Bernardi E., Sancez M., Squillero G. and Sonza Reorda M. (2006). An effective technique for minimizing the cost of processor software-based diagnosis in SoCs, Proceedings of the Conference on Design, Automation and Test in Europe, Munich, Germany, pp. 412-417.
- Bernardi P., Grosso M., Rebaudengo M. and Sonza Reorda M. (2005). Exploiting an infrastructure IP to reduce the costs of memory diagnosis in SoCs, Proceedings of the European Test Symposium, Tallinn, Estonia, pp. 202-207.
- Cheng K.-L., Tsai M.-F. and Wu C.-W. (2001). Efficient neighborhood pattern-sensitive fault test algorithms for semiconductor memories, Proceedings of the IEEE VLSI Test Symposium (VTS), Marina del Rey, CA, USA, pp. 225-237.
- Cheng K.-L., Tsai M.-F. and Wu C.-W. (2002). Neighborhood pattern sensitive fault testing and diagnostics for random access memories, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems21(11): 1328-1336.
- Cockburn B. E. (1995). Deterministic tests for detecting scrambled pattern-sensitive faults in RAMs, Proceeding IEEE International Workshop on Memory Technology, Design and Testing (MTDT 95), San Jose, CA, USA, pp. 117-122.
- Franklin M. and Saluja K. K. (1996). Testing reconfigured RAM's and scrambled address RAM's for pattern sensitive faults, IEEE Transactions on Computer-Aided Design of Integrated Circuits15(9): 1081-1087.
- Gilbert E. N. (1958). Gray codes and paths on the n-cube, Bell System Technical Journal37: 815-826.
- Goor A. J. v. d. (1991). Testing Semiconductor Memories: Theory and Practice, John Wiley & Sons, Chichester.
- Gray F. (1958). Pulse code communication, U. S. Patent 2,632,058.
- Hayes J. P. (1975). Detection of pattern sensitive faults in random access memories, IEEE Transactions on Computers24(2): 150-157.
- Hayes J. P. (1980). Testing memories for single cell pattern sensitive fault, IEEE Transactions on Computers29(2): 249-254.
- Li J.-F. (2007). Transparent-test methodologies for random access memories without/with ECC, Transactions on Computer-Aided Design of Integrated Circuits and Systems26(10): 1888-1983.
- Niggemeyer D., Redeker M. and Otterstedt J. (1998). Integration of non-classical faults in standard march tests, Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing, San Jose, CA, USA, pp. 91-96.
- Niggemeyer D., Redeker M. and Rudnick E. (2000). Diagnostic testing of embedded memories based on output tracing, Proceedings of the IEEE International Workshop on Memory Technology, Design and Testing, San Jose, CA, USA, pp. 113-118.
- Pomeranz I. and Reddy S. M. (2006). Fault detection by output response comparison of identical circuits using half-frequency compatible sequences, Proceedings of the International Test Conference, Santa Clara, CA, USA, pp. 202-207.
- Savage C. (1997). A survey of combinatorial Gray codes, SIAM Review39(4): 605-629.
- Sokol B. and Yarmolik S. V. (2006). Address sequence for March tests to detect pattern sensitive faults, Proceedings of the 3rd IEEE International Workshop on Electronic Design Test & Applications (DELTA'06), Kuala Lumpur, Malaysia, pp. 354-357.
- Suk D. S. and Reddy S. M. (1980). Test procedures for a class of pattern sensitive faults in semiconductor random access memories, IEEE Transactions on Computers29(6): 419-429.
- Yarmolik S. V. (2006). Gray code with maximum of Hamming distance, Proceedings of the 4th International Science-Practice Forum on Information Technologies and Cybernetics, Dnipropetrovsk, Ukraine, p. 77.
- Yarmolik S. V. and Sokol B. (2006). Optimal memory address seeds for pattern sensitive faults detection, Proceedings of the IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'2006), Prague, Czech Republic, pp. 220-221.
- Yarmolik S. V. and Yarmolik V. N. (2006a). Memory pattern sensitive faults detection using multiple runs of March tests, Informatics1(9): 104-113.
- Yarmolik V. N., Klimets Y. and Demidenko S. (1998). March PS(23n) test for DRAM pattem sensitive faults, Proceedings of the 7th IEEE Asian Test Symposium (ATS), Singapore, pp. 354-351.
- Yarmolik V. N. and Yarmolik S. V. (2006b). Address sequences for multiple run march tests, Automatic Control and Computer Sciences5: 59-68.