Address Sequences and Backgrounds with Different Hamming Distances for Multiple Run March Tests

Yarmolik, Svetlana

doi:10.2478/v10006-008-0030-y

Abstract

It is widely known that pattern sensitive faults are the most difficult faults to detect during the RAM testing process. One of the techniques which can be used for effective detection of this kind of faults is the multi-background test technique. According to this technique, multiple-run memory test execution is done. In this case, to achieve a high fault coverage, the structure of the consecutive memory backgrounds and the address sequence are very important. This paper defines requirements which have to be taken into account in the background and address sequence selection process. A set of backgrounds which satisfied those requirements guarantee us to achieve a very high fault coverage for multi-background memory testing.

References

Bernardi E., Sancez M., Squillero G. and Sonza Reorda M. (2006). An effective technique for minimizing the cost of processor software-based diagnosis in SoCs, Proceedings of the Conference on Design, Automation and Test in Europe, Munich, Germany, pp. 412-417.
Search in Google Scholar
Bernardi P., Grosso M., Rebaudengo M. and Sonza Reorda M. (2005). Exploiting an infrastructure IP to reduce the costs of memory diagnosis in SoCs, Proceedings of the European Test Symposium, Tallinn, Estonia, pp. 202-207.
Search in Google Scholar
Cheng K.-L., Tsai M.-F. and Wu C.-W. (2001). Efficient neighborhood pattern-sensitive fault test algorithms for semiconductor memories, Proceedings of the IEEE VLSI Test Symposium (VTS), Marina del Rey, CA, USA, pp. 225-237.
Search in Google Scholar
Cheng K.-L., Tsai M.-F. and Wu C.-W. (2002). Neighborhood pattern sensitive fault testing and diagnostics for random access memories, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems21(11): 1328-1336.10.1109/TCAD.2002.804101
Search in Google Scholar
Cockburn B. E. (1995). Deterministic tests for detecting scrambled pattern-sensitive faults in RAMs, Proceeding IEEE International Workshop on Memory Technology, Design and Testing (MTDT 95), San Jose, CA, USA, pp. 117-122.
Search in Google Scholar
Franklin M. and Saluja K. K. (1996). Testing reconfigured RAM's and scrambled address RAM's for pattern sensitive faults, IEEE Transactions on Computer-Aided Design of Integrated Circuits15(9): 1081-1087.10.1109/43.536714
Search in Google Scholar
Gilbert E. N. (1958). Gray codes and paths on the n-cube, Bell System Technical Journal37: 815-826.10.1002/j.1538-7305.1958.tb03887.x
Search in Google Scholar
Goor A. J. v. d. (1991). Testing Semiconductor Memories: Theory and Practice, John Wiley & Sons, Chichester.
Search in Google Scholar
Gray F. (1958). Pulse code communication, U. S. Patent 2,632,058.
Search in Google Scholar
Hayes J. P. (1975). Detection of pattern sensitive faults in random access memories, IEEE Transactions on Computers24(2): 150-157.10.1109/T-C.1975.224182
Search in Google Scholar
Hayes J. P. (1980). Testing memories for single cell pattern sensitive fault, IEEE Transactions on Computers29(2): 249-254.10.1109/TC.1980.1675556
Search in Google Scholar
Li J.-F. (2007). Transparent-test methodologies for random access memories without/with ECC, Transactions on Computer-Aided Design of Integrated Circuits and Systems26(10): 1888-1983.10.1109/TCAD.2007.895772
Search in Google Scholar
Niggemeyer D., Redeker M. and Otterstedt J. (1998). Integration of non-classical faults in standard march tests, Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing, San Jose, CA, USA, pp. 91-96.
Search in Google Scholar
Niggemeyer D., Redeker M. and Rudnick E. (2000). Diagnostic testing of embedded memories based on output tracing, Proceedings of the IEEE International Workshop on Memory Technology, Design and Testing, San Jose, CA, USA, pp. 113-118.
Search in Google Scholar
Pomeranz I. and Reddy S. M. (2006). Fault detection by output response comparison of identical circuits using half-frequency compatible sequences, Proceedings of the International Test Conference, Santa Clara, CA, USA, pp. 202-207.
Search in Google Scholar
Savage C. (1997). A survey of combinatorial Gray codes, SIAM Review39(4): 605-629.10.1137/S0036144595295272
Search in Google Scholar
Sokol B. and Yarmolik S. V. (2006). Address sequence for March tests to detect pattern sensitive faults, Proceedings of the 3rd IEEE International Workshop on Electronic Design Test & Applications (DELTA'06), Kuala Lumpur, Malaysia, pp. 354-357.
Search in Google Scholar
Suk D. S. and Reddy S. M. (1980). Test procedures for a class of pattern sensitive faults in semiconductor random access memories, IEEE Transactions on Computers29(6): 419-429.10.1109/TC.1980.1675601
Search in Google Scholar
Yarmolik S. V. (2006). Gray code with maximum of Hamming distance, Proceedings of the 4th International Science-Practice Forum on Information Technologies and Cybernetics, Dnipropetrovsk, Ukraine, p. 77.
Search in Google Scholar
Yarmolik S. V. and Sokol B. (2006). Optimal memory address seeds for pattern sensitive faults detection, Proceedings of the IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'2006), Prague, Czech Republic, pp. 220-221.
Search in Google Scholar
Yarmolik S. V. and Yarmolik V. N. (2006a). Memory pattern sensitive faults detection using multiple runs of March tests, Informatics1(9): 104-113.
Search in Google Scholar
Yarmolik V. N., Klimets Y. and Demidenko S. (1998). March PS(23n) test for DRAM pattem sensitive faults, Proceedings of the 7th IEEE Asian Test Symposium (ATS), Singapore, pp. 354-351.
Search in Google Scholar
Yarmolik V. N. and Yarmolik S. V. (2006b). Address sequences for multiple run march tests, Automatic Control and Computer Sciences5: 59-68.10.1134/S000511790704011X
Search in Google Scholar

Address Sequences and Backgrounds with Different Hamming Distances for Multiple Run March Tests

Abstract

Paradigm

My account