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A Novel and Ultra-Efficient Design of Reversible Quantum Vedic Multiplier Cover

A Novel and Ultra-Efficient Design of Reversible Quantum Vedic Multiplier

Open Access
|Dec 2025

Figures & Tables

Figure 1.

Toffoli gates: (a) T1 (k1), (b) T2 (k1, k2), (c) T3 (k1, k2, k3), (d) quantum layout of T3 (k1, k2, k3).
Toffoli gates: (a) T1 (k1), (b) T2 (k1, k2), (c) T3 (k1, k2, k3), (d) quantum layout of T3 (k1, k2, k3).

Figure 2.

Parity-preserving blocks (a) Toffoli-based L-block, (b) NCV-based L-block [22], (c) Toffoli-based A-block, (d) NCV-based A-block [22], and (e) Toffoli-based N2-block [33].
Parity-preserving blocks (a) Toffoli-based L-block, (b) NCV-based L-block [22], (c) Toffoli-based A-block, (d) NCV-based A-block [22], and (e) Toffoli-based N2-block [33].

Figure 3.

NCV library.
NCV library.

Figure 4.

Rules (a) rule 1, (b) rule2, (c) rule3, and (d) integrated 2-qubits.
Rules (a) rule 1, (b) rule2, (c) rule3, and (d) integrated 2-qubits.

Figure 5.

Suggested Q-block (a) Toffoli layout, (b) NCV layout, (c) optimized NCV layout.
Suggested Q-block (a) Toffoli layout, (b) NCV layout, (c) optimized NCV layout.

Figure 6.

Depicts the proposed Q-block in the IBM platform.
Depicts the proposed Q-block in the IBM platform.

Figure 7.

Measurement of Q-block qubits.
Measurement of Q-block qubits.

Figure 8.

Orbital representation of 2×2 Vedic multiplier [54].
Orbital representation of 2×2 Vedic multiplier [54].

Figure 9.

Toffoli layout of the proposed 2×2 Vedic multiplier.
Toffoli layout of the proposed 2×2 Vedic multiplier.

Figure 10.

NCV layout of the proposed 2×2 Vedic multiplier.
NCV layout of the proposed 2×2 Vedic multiplier.

Figure 11.

Depicts the proposed 2×2 Vedic multiplier in the IBM platform.
Depicts the proposed 2×2 Vedic multiplier in the IBM platform.

Figure 12.

Measurement process of qubits in a 2×2 Vedic multiplier configuration.
Measurement process of qubits in a 2×2 Vedic multiplier configuration.

Figure 13.

Circuit View of 4-bit RCA presented in [33].
Circuit View of 4-bit RCA presented in [33].

Figure 14.

Proposed 4-bit Vedic multiplier.
Proposed 4-bit Vedic multiplier.

Figure 15.

Proposed RCA (a) 8-bit and (b) 16-bit.
Proposed RCA (a) 8-bit and (b) 16-bit.

Figure 16.

Proposed 8-bit Vedic multiplier.
Proposed 8-bit Vedic multiplier.

Figure 17.

Proposed 16-bit Vedic multiplier.
Proposed 16-bit Vedic multiplier.

Figure 18.

Graphical view of the suggested design enhancement.
Graphical view of the suggested design enhancement.

A comparison of various 2×2 Vedic multipliers_

DesignsCIQCGCGOCNOT-V/V+ count
In [29]1642101650
In [30]#11640101650
In [30]#2103471044
In [30]#39317939
In [31]8306837
In [32]8295837
In [33]7275735
Proposed6253633
imp% in [29]62.5040.4770.0062.5034.00
imp% in [30]#162.5037.5070.0062.5034.00
imp% in [30]#240.0026.4757.1440.0025.00
imp% in [30]#333.3319.3557.1433.3315.38
imp% in [31]25.0016.6650.0025.0010.81
imp% in [32]25.0013.7940.0025.0010.81
imp% in [33]14.287.4040.0014.285.71
Average saving37.5123.0954.8937.5119.38
DOI: https://doi.org/10.2478/qic-2025-0030 | Journal eISSN: 3106-0544 | Journal ISSN: 1533-7146
Language: English
Page range: 552 - 567
Submitted on: Apr 1, 2025
|
Accepted on: Oct 11, 2025
|
Published on: Dec 31, 2025
In partnership with: Paradigm Publishing Services
Publication frequency: 1 issue per year

© 2025 Mojtaba Noorallahzadeh, Mohammad Mosleh, published by Cerebration Science Publishing Co., Limited
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.