Figure 1.
Toffoli gates: (a) T1 (k1), (b) T2 (k1, k2), (c) T3 (k1, k2, k3), (d) quantum layout of T3 (k1, k2, k3).
Figure 2.
Parity-preserving blocks (a) Toffoli-based L-block, (b) NCV-based L-block [22], (c) Toffoli-based A-block, (d) NCV-based A-block [22], and (e) Toffoli-based N2-block [33].
Figure 3.
NCV library.
Figure 4.
Rules (a) rule 1, (b) rule2, (c) rule3, and (d) integrated 2-qubits.
Figure 5.
Suggested Q-block (a) Toffoli layout, (b) NCV layout, (c) optimized NCV layout.
Figure 6.
Depicts the proposed Q-block in the IBM platform.
Figure 7.
Measurement of Q-block qubits.
Figure 8.
Orbital representation of 2×2 Vedic multiplier [54].
Figure 9.
Toffoli layout of the proposed 2×2 Vedic multiplier.
Figure 10.
NCV layout of the proposed 2×2 Vedic multiplier.
Figure 11.
Depicts the proposed 2×2 Vedic multiplier in the IBM platform.
Figure 12.
Measurement process of qubits in a 2×2 Vedic multiplier configuration.
Figure 13.
Circuit View of 4-bit RCA presented in [33].
Figure 14.
Proposed 4-bit Vedic multiplier.
Figure 15.
Proposed RCA (a) 8-bit and (b) 16-bit.
Figure 16.
Proposed 8-bit Vedic multiplier.
Figure 17.
Proposed 16-bit Vedic multiplier.
Table 1.
A comparison of various 2×2 Vedic multipliers.
| Designs | CI | QC | GC | GO | CNOT-V/V+ count |
|---|---|---|---|---|---|
| In [29] | 16 | 42 | 10 | 16 | 50 |
| In [30]#1 | 16 | 40 | 10 | 16 | 50 |
| In [30]#2 | 10 | 34 | 7 | 10 | 44 |
| In [30]#3 | 9 | 31 | 7 | 9 | 39 |
| In [31] | 8 | 30 | 6 | 8 | 37 |
| In [32] | 8 | 29 | 5 | 8 | 37 |
| In [33] | 7 | 27 | 5 | 7 | 35 |
| Proposed | 6 | 25 | 3 | 6 | 33 |
| imp% in [29] | 62.50 | 40.47 | 70.00 | 62.50 | 34.00 |
| imp% in [30]#1 | 62.50 | 37.50 | 70.00 | 62.50 | 34.00 |
| imp% in [30]#2 | 40.00 | 26.47 | 57.14 | 40.00 | 25.00 |
| imp% in [30]#3 | 33.33 | 19.35 | 57.14 | 33.33 | 15.38 |
| imp% in [31] | 25.00 | 16.66 | 50.00 | 25.00 | 10.81 |
| imp% in [32] | 25.00 | 13.79 | 40.00 | 25.00 | 10.81 |
| imp% in [33] | 14.28 | 7.40 | 40.00 | 14.28 | 5.71 |
| Average saving | 37.51 | 23.09 | 54.89 | 37.51 | 19.38 |
Figure 18.
Graphical view of the suggested design enhancement.