A Compact Design of a Two-stage Piecewise Linear ADC Used for Sensor Linearity Improvement

Accurate sensor measurements are essential in modern measurement systems, yet sensor nonlinearity remains a significant challenge affecting overall accuracy. Several techniques can address this issue, but the use of a two-stage piecewise linear analog-to-digital converter (ADC) has proven highly effective for sensor linearization [1],[2],[3],[4],[5],[6],[7],[8],[9],[10]. By integrating sensor linearization and signal digitization into a single process, the mentioned ADC reduces processing time, power consumption and implementation costs, making it highly suitable for resource-constrained measurement applications. Because of these advantages, two-stage piecewise linear ADCs are widely used for the linearization of various sensor types, including NTC thermistors, Pt100 sensors, angular position sensors, and humidity sensors [1],[2],[3],[4],[5],[6],[7], [11].

Other sensor linearization techniques often suffer from limitations such as high memory and computational demands, particularly when the sensor's transfer function is unknown [12], [13]. Although neural networks have been explored as an alternative approach, their implementation requires large amounts of training data and significant computational resources [12], [14], [15]. In contrast, the two-stage piecewise linear ADC performs sensor linearization without these overheads, providing a more resource-efficient solution.

The traditional two-stage piecewise linear ADC architecture uses a separate ADC for each conversion stage. Linearization is performed in the first stage with a flash ADC whose transfer function approximates, in a piecewise linear manner, the inverse of the sensor's static transfer function. The input range of the flash ADC is divided into segments of varying widths (nonuniform segments), each bounded by specific points called break voltages. These break voltages are used as reference voltages for the comparators in the flash ADC. In the second conversion stage, a linear ADC is used, which may be implemented as a flash ADC or as another type, such as a successive approximation (SAR) ADC. Within the second conversion stage, each input voltage sample is further mapped to a uniform sub-segment within the corresponding nonuniform segment defined earlier. Although linearization is not performed in this stage, the subdivision improves both resolution and measurement accuracy. The resolutions of the first and second conversion stages are usually not equal. It is generally preferable for the first stage to have higher resolution, as sensor linearization primarily occurs at this stage. However, increasing the resolution of the first stage also increases implementation complexity.

An advantage of a two-stage piecewise linear ADC is its adaptability to different sensor types by adjusting the comparators' reference voltages in the flash ADC using a resistor ladder network. Given this advantage, reducing the complexity, power consumption, and implementation costs of the two-stage piecewise linear ADC remains an important research objective.

This paper presents a compact and cost-effective design for a two-stage piecewise linear ADC, in which both conversion stages are performed using a single flash ADC, with the addition of two comparators, one at the start of each conversion stage. This design strategy significantly reduces the overall comparator and resistor counts. Notably, in the proposed design, each additional comparator contributes one bit of resolution, unlike the traditional approach, where increasing the resolution of a conversion stage by one bit doubles the number of comparators.

This paper proposes a compact two-stage piecewise linear ADC designed to improve sensor linearity and increase measurement accuracy. The key contribution of the proposed design is a substantial reduction in component count compared to traditional architecture. Unlike traditional two-stage piecewise linear ADC implementation (see Fig. 1), the proposed approach achieves the same total resolution with significantly fewer comparators by reusing a single flash ADC for both conversion stages and incorporating only two additional comparators. Although several methods for increasing resolution with fewer comparators have been explored in the literature [5], [6], [16], the proposed design achieves greater compactness by further reducing the number of resistors required in the flash ADC's resistor ladder network [17], [18]. Since comparators are among the most power-consuming components in flash ADC circuits [19], reducing their number, as well as the number of resistors, decreases circuit complexity, power consumption and implementation costs. This makes the proposed design a highly efficient alternative to the traditional two-stage piecewise linear ADC design.

Fig. 1.

Traditional 6-bit two-stage piecewise linear ADC using a separate 3-bit flash ADC in each conversion stage.

Fig. 1 illustrates a traditional 6-bit two-stage piecewise linear ADC, where each conversion stage uses a separate flash ADC. It is well established that the implementation of an N-bit flash ADC requires 2^N resistors and 2^N−1 comparators [17], [18]. In the example shown in Fig. 1, two 3-bit flash ADCs are used, resulting in a total of 14 comparators (7 per stage) and 16 resistors across two independent resistor ladder networks. The input range of the first conversion stage spans from 0 V to V_MAX (V_MAX = f(x_MAX), where f(x) is the sensor's transfer function and x_MAX is the maximum value of the measured parameter x), and the current sample of the input voltage signal is denoted as V_IN. In this example, both stages are configured with the same resolution; however, this configuration is not a requirement in practical implementations. Typically, the first stage is implemented with a lower resolution than the second due to the complexity of designing a nonuniform resistor ladder network (R₁ to R₈), which determines the reference voltages for the comparators. However, higher resolution in the first stage is desirable, as linearization is performed at that point.

The second stage is simpler to implement, using a uniform resistor ladder network composed of identical resistors R. This allows the use of uniform off-the-shelf ADCs in the second stage (e.g., flash, SAR, or other types) [1],[2],[3],[4], [6], [11], [20]. Equal resolutions of 3 bits per conversion stage were chosen in the traditional architecture, shown in Fig. 1, to enable a direct comparison with the compact 6-bit two-stage piecewise linear ADC proposed in this paper.

The proposed 6-bit architecture, shown in Fig. 2, differs fundamentally by replacing two 3-bit flash ADCs with a single 2-bit flash ADC and two additional comparators. Each of these comparators (C₁ and C₅) independently contributes one bit of resolution. Determining the nonuniform reference voltages of all comparators V_i in the first conversion stage, including the reference voltage V_REF1 of the additional comparator C₁ (see Fig. 2), is a critical aspect of the design. These voltages can be determined using the following equations: (1) Vi=f(xi),i=1,2,…,2n/n−1, \matrix{{{V_i} = f({x_i}),} & {i = 1,2, \ldots,{2^{n/n}} - 1,} \cr} (2) VREF1=f(xi),i=2n/2−1, \matrix{{{V_{{\rm{REF}}1}} = f({x_i}),} & {i = {2^{n/2 - 1}},} \cr} for the corresponding values x_i at the sensor input, defined as: (3) xi=i⋅xMAX2n/2,i=1,2,…,2n/2−1. \matrix{{{x_i} = i \cdot {{{x_{{\rm{MAX}}}}} \over {{2^{n/2}}}},} & {i = 1,2, \ldots,{2^{n/2}} - 1} \cr}.

Fig. 2.

Compact 6-bit two-stage piecewise linear ADC using one 2-bit flash ADC and two additional comparators (C₁ and C₅).

The resistor values used to set these reference voltages are determined as follows: (4) Ri=RtVMAX⋅Vi−∑j=1i−1Rj,i=1,2,…,2n/2, \matrix{{{R_i} = {{{R_{\rm{t}}}} \over {{V_{{\rm{MAX}}}}}} \cdot {V_i} - \sum\limits_{j = 1}^{i - 1} {{R_j}},} & {i = 1,2, \ldots,{2^{n/2}}} \cr}, where R_t represents the total resistance of the resistor ladder network used in the first conversion stage.

In the proposed two-stage piecewise linear ADC (see Fig. 2), the initial step is to set the reference voltage V_REF1 of comparator C₁, which corresponds to the central reference voltage V₄. The input sample V_IN is captured at a moment determined by the timing generator signal t₁. The sample is then routed to the input of comparator C₁. Comparator C₁ evaluates whether the input sample V_IN is greater than or less than the voltage V_REF1. If V_IN > V_REF1, the output bit B′₂ = 1; otherwise, B′₂ = 0. This bit controls three 2-to-1 analog multiplexers, which route either the reference voltages less than V_REF1 or those greater than V_REF1 to the inputs of the flash ADC comparators, depending on the value of V_IN. As a result, the input range of the flash ADC is dynamically selected as either from 0 to V_REF1 when B′₂ = 0, or from V_REF1 to V_MAX when B′₂ = 1. After selecting the relevant reference voltages and comparing them against V_IN, a 3-bit code is generated and then converted into a 2-bit binary code by a priority encoder, producing the output bits B′₁ and B′₀. The combined bits B′₂B′₁B′₀ represent the result of the coarse stage and are stored in the output register at the timing signal t₂. These bits also control two 8-to-1 analog multiplexers, which select the corresponding lower V_L and upper V_U reference (break) voltages representing the boundaries of the nonuniform segment to which the input sample V_IN belongs. Simultaneously, V_L and V_U define the input range for the second stage of conversion.

Similar to the first stage, the second stage starts with an additional comparator, C₅, placed before the flash ADC. The reference voltage V_REF2 of comparator C₅ represents the midpoint between V_L and V_U, defined as: (5) VREF2=VL+VU2. {V_{{\rm{REF}}2}} = {{{V_{\rm{L}}} + {V_{\rm{U}}}} \over 2}.

This voltage is generated using two resistors of equal value R, forming a passive voltage divider as shown in Fig. 2. Comparator C₅ then determines whether the input sample V_IN lies above or below V_REF2, producing the bit B″₂. The output bit of comparator C₅ controls the operation of two 2-to-1 analog multiplexers. These multiplexers dynamically define the input range of the same flash ADC used in the first conversion stage. When B″₂ = 0, the input range of the flash ADC spans from V_L (lower bound) to V_REF2 (upper bound).

Conversely, when B″₂ = 1, the input range shifts from V_REF2 (lower bound) to V_U (upper bound). In future work, the proposed two-stage piecewise linear ADC may be redesigned to eliminate comparator C₅ and integrate its function into comparator C₁, along with a circuit modification that enables switching the reference voltage between V_REF1 and V_REF2, resulting in a small reduction in conversion speed.

In the second conversion stage, the resistor ladder network consists of four equal-value resistors R instead of eight, since only three uniformly spaced reference voltages are required, compared to the seven nonuniform ones needed in the first stage. A network of switches, controlled by timing signal t₃, selects the corresponding reference voltages: nonuniform reference voltages V₁ to V₇ for the first conversion stage, or uniform reference voltages V₂₁, V₂₂, and V₂₃ for the second stage.

Fig. 3 illustrates the method for determining the break voltages of the nonuniform segments (V₁ to V₇) in the first conversion stage and the break voltages of the uniform sub-segments (V₂₁, V₂₂, and V₂₃) in the second conversion stage. By dividing the sensor's input range, which spans from 0 to x_MAX, into eight equal parts (for n = 3 bits) and mapping the boundaries of these divisions onto the corresponding values on the y-axis, the break voltages of the eight nonuniform segments are obtained. Each nonuniform segment is encoded with a corresponding 3-bit binary code ranging from 000 to 111. Depending on the input voltage sample V_IN, one of these nonuniform segments serves as the input range for the second, uniform conversion stage (between V_L and V_U). The right side of Fig. 3 presents a detailed view explaining how the uniform break voltages V₂₁, V₂₂, and V₂₃ are determined in the second conversion stage (for example, when V_L = 0 V and V_U = V₁). In this case, the reference voltage V_REF2 also influences the values of the break voltages for the uniform sub-segments, as it defines the input range for the flash ADC in the second stage. Each of these uniform sub-segments is also represented by a unique 3-bit code word, ranging from 000 to 111. The values of the break (reference) voltages V_2j in the second conversion stage can be determined as follows:

• 1) (6) VIN<VREF2,(B″2=0), \matrix{{{V_{{\rm{IN}}}} < {V_{{\rm{REF}}2}},} & {({{B''}_2} = 0)} \cr},

  (7) V2j=VL+j⋅VREF2−VL2n/2−1,j=1,2,…,2n/2−1−1, \matrix{{{V_{2j}} = {V_{\rm{L}}} + j \cdot {{{V_{{\rm{REF}}2}} - {V_{\rm{L}}}} \over {{2^{n/2 - 1}}}},} & {j = 1,2, \ldots,{2^{n/2 - 1}} - 1} \cr},

  or

  2) (8) VIN<VREF2,(B″2=1), \matrix{{{V_{{\rm{IN}}}} < {V_{{\rm{REF}}2}},} & {({{B''}_2} = 1)} \cr},

  (9) V2j=VREF2+j⋅VU−VREF22n/2−1,j=1,2,…,2n/2−1−1. \matrix{{{V_{2j}} = {V_{{\rm{REF}}2}} + j \cdot {{{V_{\rm{U}}} - {V_{{\rm{REF}}2}}} \over {{2^{n/2 - 1}}}},} & {j = 1,2, \ldots,{2^{n/2 - 1}} - 1} \cr}.

Fig. 3.

Illustration of a method for determining the break voltages of nonuniform segments (V₁ to V₇) in the first conversion stage and the break voltages of uniform sub-segments (V₂₁, V₂₂, and V₂₃) in the second conversion stage (enlarged detail on the right).

Once the switches are closed under the control of timing signal t₃, the new reference voltages V₂₃, V₂₂, and V₂₁ are applied to the inputs of comparators C₂, C₃, and C₄, respectively. This is followed by the conversion of a 3-bit code into a 2-bit binary code using a 2-bit priority encoder, which produces the final two bits of the digital output, B″₁ and B″₀. When the full 3-bit code B″₂B″₁B″₀ is latched into the output register at the moment defined by timing signal t₄, the conversion process is complete, resulting in a digital representation of the input voltage sample V_IN.

It is important to emphasize that after converting the complete 6-bit code B′₂B′₁B′₀B″₂B″₁B″₀ back to an analog voltage, and consequently to the corresponding value of the measured parameter, a significantly smaller discrepancy can be expected between the actual and measured values [1],[2],[3],[4],[5],[6],[7]. In other words, the measurement error caused by the sensor's nonlinearity can be considerably reduced with the proposed linearization circuit.

This section provides a comparative analysis of how the resolution of a two-stage piecewise linear ADC affects the comparator and resistor requirements in both traditional and proposed compact designs. For the traditional two-stage piecewise linear ADC, the total number of comparators n_ct and resistors n_rt can be determined using the following expressions [17], [18]: (10) nct=(2Nt−1)+(2Nt−1), {n_{{\rm{ct}}}} = ({2^{{N_{\rm{t}}}}} - 1) + ({2^{{N_{\rm{t}}}}} - 1), (11) nrt=2Nt+2Nt. {n_{{\rm{rt}}}} = {2^{{N_{\rm{t}}}}} + {2^{{N_{\rm{t}}}}}.

Here, N_t = n/2 represents the resolution of each flash ADC in the traditional two-stage configuration, where n denotes the total resolution. Each addend in both expressions corresponds to one conversion stage.

In the proposed compact two-stage piecewise linear ADC design, the total number of employed comparators n_cp is: (12) ncp=1+(2Np−1)+1. {n_{{\rm{cp}}}} = 1 + ({2^{{N_{\rm{p}}}}} - 1) + 1.

In this expression, the two addends with a value of 1 represent the additional comparators C₁ and C₅, while the addend (2^Np−1) corresponds to the number of comparators used in the flash ADC with a resolution of N_p = n/2−1. The total number of resistors used in the proposed compact design n_rp is given by: (13) nrp=2Np+1+(2+2Np), {n_{{\rm{rp}}}} = {2^{{N_{\rm{p}}} + 1}} + (2 + {2^{{N_{\rm{p}}}}}), where the first addend represents the resistors used in the resistor ladder network of the flash ADC during the first conversion stage. The second addend accounts for the two resistors forming the passive voltage divider, along with the resistors in the resistor ladder network used in the second conversion stage.

To assess the improvements introduced by the compact design compared to the traditional approach, the relative differences in comparator counts δ_c and resistor counts δ_r are computed as follows: (14) δc=(nct−ncp)nct⋅100%, {\delta_{\rm{c}}} = {{({n_{{\rm{ct}}}} - {n_{{\rm{cp}}}})} \over {{n_{{\rm{ct}}}}}} \cdot 100\%, (15) δr=(nrt−nrp)nrt⋅100%, {\delta_{\rm{r}}} = {{({n_{{\rm{rt}}}} - {n_{{\rm{rp}}}})} \over {{n_{{\rm{rt}}}}}} \cdot 100\%,

Table 1 presents key parameters for various total resolution values n, including flash ADC resolutions, N_t = n/2 for the traditional design and N_p = n/2−1 for the proposed design. It also lists comparator and resistor counts for both architectures, along with their relative differences, highlighting the hardware savings of the proposed architecture.

As the total resolution n increases, the difference in the number of comparators and resistors between the traditional and proposed two-stage piecewise linear ADC designs becomes more pronounced. As previously noted, Table 1 lists the total number of comparators n_ct and resistors n_rt for the traditional design, along with the corresponding values for the proposed compact design n_cp and n_rp across various resolution values n. It also includes the calculated relative differences in comparator counts δ_c and resistor counts δ_r between the two designs.

The numerical results clearly demonstrate a significant reduction in hardware complexity achieved by the proposed design. As the total resolution n increases, the relative differences δ_c and δ_r grow steadily. Specifically, for resolutions exceeding 14 bits, both metrics show a strong upward trend, approaching their maximum values of 75 % and 25 %, respectively. These peak values will be fully attained when the total resolution reaches 42 bits. Even at lower resolutions n, the savings in component count are considerable, highlighting the cost-effectiveness of the proposed solution. This reduction translates directly into lower manufacturing costs, improved compactness, and reduced power consumption, making the proposed two-stage piecewise linear ADC highly suitable for sensor linearization in embedded or resource-constrained systems.

It should be noted that the introduction of comparators C₁ and C₅, together with additional multiplexers, causes a certain increase in conversion time. However, this is compensated by performing linearization and analog-to-digital conversion within a single circuit, which reduces the overall time required to process the sensor output signal, as well as the associated implementation cost.

This paper presents a novel compact two-stage piecewise linear ADC that improves sensor linearity while exhibiting reduced hardware complexity. By sharing a single flash ADC between both conversion stages and introducing two additional comparators, one for each stage, the proposed design achieves the same total resolution as the traditional design but with a substantially lower component count. Analytical expressions and numerical analysis show that the proposed architecture requires significantly fewer comparators and resistors than its traditional counterpart, with the savings becoming more pronounced as total resolution increases.

The numerical results validate the advantages of the proposed compact design. At higher total resolutions, the compact design achieves up to a 75 % reduction in comparator count and up to a 25 % reduction in resistor count compared to the traditional two-stage piecewise linear ADC with the same total resolution. These reductions directly lead to lower energy consumption, reduced silicon area, and decreased manufacturing costs. Even at low and moderate resolutions, the proposed design yields notable savings, confirming its suitability for compact, low-power embedded applications. Furthermore, by combining sensor linearization with digital conversion in a single process, the two-stage piecewise linear ADC delivers improved performance in modern smart sensing systems. Overall, the results confirm that the proposed compact two-stage piecewise linear ADC is a highly efficient, scalable, and cost-effective solution for high-resolution, low-power sensor linearization.