Have a personal or library account? Click to login
Error Models of the Analog to Digital Converters Cover

Error Models of the Analog to Digital Converters

Measurement Science Review
Volume 14 (2014): Issue 2 (April 2014)
By: Linus Michaeli and  Ján Šaliga  
Open Access
|May 2014

References

  1. [1] IEEE Std. (2008). IEEE Standard for digitizing waveform recorders. 1057-2007. New York: IEEE.
    Search in Google Scholar
  2. [2] IEEE Std. (2011). IEEE Standard for terminology and test methods for analog-to-digital converters. 1241-2010. New York: IEEE.
    Search in Google Scholar
  3. [3] Arpaia, P., Daponte, P., Michaeli, L. (1999). The influence of the architecture on ADC modelling. IEEE Transactions on Instrumentation and Measurement, 48(5), 956-967.10.1109/19.799654
    Search in Google Scholar
  4. [4] Alegria, F., Arpaia, P., Daponte, P., Serra, A.C. (2002). An ADC histogram test based on smallamplitude waves. Measurement, 31 (4), 219-279.
    Search in Google Scholar
  5. [5] Vargha, B., Shoukens, J., Rolain, Y. (2001). Nonlinear model based calibration of A/D converters. In 6th Euro Workshop on ADC Modelling and Testing, 13-14 Sept. 2001, Lisbon, Portugal, 79-83.
    Search in Google Scholar
  6. [6] Janik, J.M. (2003). Estimation of A/D converter nonlinearities from complex spectrum. In 8th International Workshop on ADC Modelling and Testing, 8-10 Sept. 2003, Perugia, Italy, 205-208.
    Search in Google Scholar
  7. [7] Adamo, F., Attavissimo, F., Giasquinto, N. (2000). Measurement of ADC integral nonlinearity via DFT. In 5th International Workshop on ADC Modelling and Testing, 26-28 Sept. 2000, Vienna, Austria, 3-8.
    Search in Google Scholar
  8. [8] Adamo, F., Attivissimo, F., Giaquinto, N., Kale, I. (2007). Frequency domain analysis for dynamic nonlinearity measurement in A/D converters. IEEE Transactions on Instrumentation and Measurement, 56 (3), 760-768.10.1109/TIM.2007.894893
    Search in Google Scholar
  9. [9] Attivissimo, F., Giaquinto, N., Kale, I. (2004). INL reconstruction of A/D converters via parametric spectral estimation. IEEE Transactions on Instrumentation and Measurement, 53 (4), 940-946.10.1109/TIM.2004.831508
    Search in Google Scholar
  10. [10] Arpaia, P., Daponte, P., Rapuano, S. (2004). A state of the art on ADC modelling. Computer Standards & Interfaces, 26 (1), 31-42.10.1016/S0920-5489(03)00060-6
    Search in Google Scholar
  11. [11] Chen, T., Gielen, G. (2003). Analysis of the dynamic SFDR property of high-accuracy current-steering D/A converters. In International Symposium on Circuits and Systems, 25-28 May 2003, Bangkok, Thailand. IEEE, Vol. 1, 973-976.
    Search in Google Scholar
  12. [12] Vargha, B., Schoukens, J., Rolain, Y. (2002). Using reduced-order models in D/A converter testing. In 19th Instrumentation and Measurement Technology Conference, Anchorage, USA. IEEE, Vol. 1, 701-706.
    Search in Google Scholar
  13. [13] Hassan, I.H.S., Arabi, K., Kaminska, B. (1998). Testing digital to analog converters based on oscillation-test strategy using sigma-delta modulation. In International Conference on Computer Design - VLSI in Computers and Processors, 5-7 Oct. 1998, Austin, Texas. IEEE, 40-46.10.1109/ICCD.1998.727021
    Search in Google Scholar
  14. [14] Arpaia, P., Cennamo, F., Daponte, P., D´Apuzzo, M. (1996). A behavioural model for scan converter based transient digitizers. Measurement, 17 (2), 103-114.10.1016/0263-2241(96)00018-8
    Search in Google Scholar
  15. [15] Bjorsell, N., Handel, P. (2006). Dynamic behavior models of analog to digital converters aimed for postcorrection in wideband applications. In IMEKO World Congress : 11th Workshop on ADC Modelling and Testing, 17-22 Sept. 2006, Rio de Janeiro, Brazil.
    Search in Google Scholar
  16. [16] Medawar, S., Handel, P., Bjorsell, N., Jansson, M. (2010). Input dependent integral nonlinearity modeling for pipelined analog-digital converters. IEEE Transactions on Instrumentation and Measurement, 59 (10), 2609-2620.10.1109/TIM.2010.2045551
    Search in Google Scholar
  17. [17] Medawar, S., Handel, P., Bjorsell, N., Jansson, M. (2008). ADC characterization by dynamic integral non-linearity. In 13th Workshop on ADC Modeling and Testing, 22-24 Sept. 2008, Florence, Italy, 1-6.
    Search in Google Scholar
  18. [18] Michaeli, L., Michalko, P., Saliga, J. (2008). Unified ADC nonlinearity error model for SAR ADC. Measurement, 41 (2), 198-204.10.1016/j.measurement.2006.10.004
    Search in Google Scholar
  19. [19] Arpaia, P., Daponte, P., Michaeli, L. (1999). A dynamic error model for integrating analog-to-digital converters. Measurement, 25, 255-264.10.1016/S0263-2241(99)00010-X
    Search in Google Scholar
  20. [20] Medawar, S., Handel, P., Bjorsell, N., Jansson, M. (2011). Postcorrection of pipelined analog digital converters based on input-dependent integral nonlinearity modeling. IEEE Transactions on Instrumentation and Measurement, 60 (10), 3342-3350.10.1109/TIM.2011.2126870
    Search in Google Scholar
  21. [21] Lundin, H., Handel, P. (2014). Look-up tables, dithering and volterra series for ADC improvements. In Design, Modeling and Testing of Data Converters. Springer, 249-275.10.1007/978-3-642-39655-7_8
    Search in Google Scholar
  22. [22] Nikaeen, P. (2008). Digital compensation of dynamic acquisition errors at the front-end of ADCs. Dissertation, Stanford University, Stanford, CA, USA.
    Search in Google Scholar
  23. [23] Brigati, S., Liberali, V., Maloberti, F. (1994). Precision behavioural modelling of circuit components for data converters. In Second International Conference on Advanced A-D and D-A Conversion Techniques and their Applications, 6-8 July 1994. IEEE, 110-115.10.1049/cp:19940552
    Search in Google Scholar
  24. [24] Balestrieri, E., Daponte, P., Rapuano, S. (2004). A state of the art on ADC error compensation methods. In 21st Instrumentation and Measurement Technology Conference, 18-20 May 2004. IEEE, Vol. 1, 711-716.
    Search in Google Scholar
  25. [25] Ruan, G. (1991). A behavioral model of A/D converters using a mixed-mode simulator. In IEEE Transactions on Solid-State Circuits, 26 (3), 283-290.10.1109/4.75007
    Search in Google Scholar
  26. [26] Vargha, B., Zoltan, I. (2001). Calibration algorithm for current - output R-2R ladders. IEEE Transactions on Instrumentation and Measurement, 50 (5), 1216-1220.10.1109/19.963186
    Search in Google Scholar
  27. [27] Arpaia, P., Daponte, P., Michaeli, L. (1998). Analytical a priori approach to phase-plane modeling of SAR A/D converters. IEEE Transactions on Instrumentation and Measurement, 47 (4), 849-857.10.1109/19.744632
    Search in Google Scholar
  28. [28] Mirri, D., Iuculano, G., Filicori, F., Pasini, G., Vannini, G. (1995). Modeling of non ideal dynamic characteristics in S/H-ADC devices. In Instrumentation and Measurement Technology Conference, 24-26 April 1995. IEEE, 27.10.1109/IMTC.1995.515097
    Search in Google Scholar
  29. [29] Michaeli, L., Šaliga, J., Michalko, P. (2007). Triangular testing signal for identification of unified error model parameters. Measurement, 40 (5), 491-499.10.1016/j.measurement.2006.11.002
    Search in Google Scholar
  30. [30] Hejn, K. (1998). A behavioral model of fast AD converter. In IMEKO TC-4 : 1st International Workshop on ADC Modelling. Smolenice, Slovakia, 28-38.
    Search in Google Scholar
  31. [31] Maloberti, F. (2007). Data Converters. Springer.
    Search in Google Scholar
  32. [32] Seckin, U., Ken Yang, C. (2008). A comprehensive delay model for CMOS CML circuits. IEEE Transactions on Circuits Systems I: Regular Papers, 55 (9), 2608-2318.10.1109/TCSI.2008.920069
    Search in Google Scholar
  33. [33] Jerng, A., Sodini, C.G. (2007). A wideband ΔΣ digital-RF modulator for high data rate transmitters. IEEE Journal of Solid-State Circuits, 42 (8), 1710-1722.10.1109/JSSC.2007.900255
    Search in Google Scholar
  34. [34] Agrež, D. (2011). Quantization noise of the nonuniform exponential tracking A/D conversion. In 16th IMEKO TC4 : 2011 International Workshop on ADC Modelling, Testing and Data Converter Analysis and Design and IEEE 2011 ADC Forum, Orvieto, Italy.
    Search in Google Scholar
  35. [35] Van de Plassche, R. (2010). CMOS Integrated Analogto-Digital and Digital-to-Analog Converters. Springer.
    Search in Google Scholar
  36. [36] Haenzsche, S., Henker, S., Schuffny, R. (2010). Modelling of capacitor mismatch and non-linearity effects in charge redistribution ADCs. In Mixed Design of Integrated Circuits and Systems : 17th International Conference, 24-26 June 2010. IEEE, 300-305.
    Search in Google Scholar
  37. [37] Mashhadi, S.B., Pishbin, S.I. (2011). Efficient modeling and analysis of switch-induced error voltage in high resolution SAR ADCs. In 18th IEEE International Conference on Electronics, Circuits and Systems, 11-14 Dec. 2011. IEEE, 208- 211.10.1109/ICECS.2011.6122250
    Search in Google Scholar
  38. [38] Kochan, R., Klym, H. (2010). Simulation model of delta-sigma modulator. In International Conference on Modern Problems of Radio Engineering, Telecommunications and Computer Science, 23-27 Febr. 2010. IEEE, 44.
    Search in Google Scholar
  39. [39] Zhang, S., Ding, L., Xu, J., Zhang, F., Wang, S., Chang, Y. (2010). Digital background calibration of MDAC stage gain error and DAC error in pipelined ADC. In 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, 1-4 Nov. 2010. IEEE, 251-253.10.1109/ICSICT.2010.5667773
    Search in Google Scholar
  40. [40] Fan Bing, Wang Donghui, Zhang Tiejun, Hou Chaohuan. (2007). Modeling and simulation of an open-loop architecture ADC. In 7th International Conference on ASIC, 22-25 Oct. 2007. IEEE, 1193-1196.
    Search in Google Scholar
  41. [41] Centurelli, F., Monsurro, P., Trifiletti, A. (2010). Behavioral modeling for calibration of pipeline analog-to-digital converters. IEEE Transactions on Circuits and Systems I: Regular Papers, 57 (6), 1255-1264.10.1109/TCSI.2009.2033532
    Search in Google Scholar
  42. [42] Wegener, C., Kennedy, M.P. (2002). Implementation of model-based testing for medium- to high-resolution Nyquist-rate ADCs. In International Test Conference, 10 Oct. 2002. IEEE, 851-860.10.1109/TEST.2002.1041839
    Search in Google Scholar
  43. [43] Centurelli, F., Monsurro, P., Trifiletti, A. (2007). A distortion model for pipeline Analog-to-Digital converters. In IEEE International Symposium on Circuits and Systems, 27-30 May 2007. IEEE, 3387-3390.10.1109/ISCAS.2007.378294
    Search in Google Scholar
  44. [44] Arpaia, P., Inglese, V., Spiezia, G., Tiso, S. (2009). Surface-response-based modeling of digitizers: A case study on a fast digital integrator at CERN. IEEE Transactions on Instrumentation and Measurement, 58(6), 1919-1928.10.1109/TIM.2008.2005855
    Search in Google Scholar
  45. [45] Duan, J., Jin, L., Chen, D. (2010). INL based dynamic performance estimation for ADC BIST. In IEEE International Symposium on Circuits and Systems, 30 May - 2 June 2010. IEEE, 3028-3031.10.1109/ISCAS.2010.5538005
    Search in Google Scholar
  46. [46] Kumar, R., Taggart, D., Chen, C., Goo, G., Krikorian, Y. (2004). Modeling, simulation, and analysis of analog-to-digital converters for wireless communication broadband satellite systems. In IEEE 60th Vehicular Technology Conference, 26-29 Sept. 2004. IEEE, Vol. 6, 4221-4227.
    Search in Google Scholar
  47. [47] Parkey, C.R., Mikhael, W.B., Chester, D.B., Hunter, M.T. (2011). Modeling of jitter and its effects on time interleaved ADC conversion. In IEEE AUTOTESTCON, 12-15 Sept. 2011. IEEE, 367-372.10.1109/AUTEST.2011.6058747
    Search in Google Scholar
  48. [48] Folkesson, K., Svensson, C., Eklund, J.-E. (2001). Modeling of dynamic errors in algorithmic A/D converters. In IEEE International Symposium on Circuits and Systems. IEEE, Vol. 5, 455-458.
    Search in Google Scholar
  49. [49] Medawar, S., Murmann, B., Handel, P., Bjorsell, N., Jansson, M. (2014). Integral nonlinearity modeling and calibration of measured and synthetic pipeline Analogto Digital Converters. IEEE Transactions on Instrumentation and Measurement, 63 (3), 502-511.10.1109/TIM.2013.2282002
    Search in Google Scholar
  50. [50] De Vito, L., Lundin, H., Rapuano, S. (2006). Bayesian calibration of a lookup table for ADC error correction. IEEE Transactions on Instrumentation and Measurement, 56 (3), 873-878.
    Search in Google Scholar
  51. [51] Wegener, C., Kennedy, M.P. (2003). Linear modelbased error identification and calibration for data converters. In Design, Automation and Test in Europe Conference and Exhibition. IEEE, 630-635.
    Search in Google Scholar
DOI: https://doi.org/10.2478/msr-2014-0010 | Journal eISSN: 1335-8871
Journal RSS Feed
Language: English
Page range: 62 - 77
Submitted on: Jan 19, 2014
|
Accepted on: Apr 10, 2014
|
Published on: May 8, 2014
Published by: Slovak Academy of Sciences, Institute of Measurement Science
In partnership with: Paradigm Publishing Services
Publication frequency: Volume open
Keywords:
ADC testing,
ADC modeling,
data correction
Related subjects:
Engineering,
Electrical engineering,
Control engineering, metrology and testing

© 2014 Linus Michaeli, Ján Šaliga, published by Slovak Academy of Sciences, Institute of Measurement Science
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 3.0 License.

Previous articleVolume 14 (2014): Issue 2 (April 2014)Next article