Noise Immunity of the Fibonacci Counter with the Fractal Decoder Device for Telecommunication Systems

Matsenko, S.; Borysenko, O.; Spolitis, S.; Bobrovs, V.

doi:10.2478/lpts-2019-0027

Abstract

The paper presents the improved method of noise immune Fibonacci counting in the minimal form of representation. The method was tested and investigated in the developed noise immune pulse counter based on a minimal form of Fibonacci code with a fractal decoding device. The proposed device, which is simulated in the NI Multisim software, possesses a homogenous structure, increased noise immunity, performance and detection of bit errors in the process of its operation.

References

1. Stakhov, A. (2017). Numeral systems with irrational bases for mission-critical applications. Singapore; New Jersey: World Scientific Publishing Co. Pte. Ltd.10.1142/10671
Search in Google Scholar Back to article
2. Stakhov, A. (2012). Fibonacci and golden proportion codes as an alternative to the binary numeral system. Germany: Academic Publishing.
Search in Google Scholar Back to article
3. Hoggatt, V. E. (1969). Fibonacci and Lucas numbers. Boston: Houghton Mifflin.
Search in Google Scholar Back to article
4. Vorobyov, N. (1978). Fibonacci numbers. Moscow: Nauka.
Search in Google Scholar Back to article
5. Stakhov, A., Borisenko, A., & Matsenko, S. (2014). Fibonacci Counter based on Zeckendorf’s Theorem (Boolean Realization). Visual Mathematics, 16(2), 19.
Search in Google Scholar Back to article
6. United States Patent No. US8983023 B2. (2015). Digital Self-Gated Binary Counter, Gupta, N., Agarval A., Goyal, G., No. US 13/935,552; declared: 04.07.2013; published: 17.03.2015.
Search in Google Scholar Back to article
7. Yeh, C.-H. (2000). Designs of counters with near minimal counting / sampling period and hardware complexity. Pacific Grove, CA, USA.
Search in Google Scholar Back to article
8. Thamaraiselvan, K. A. (2013). High Speed CMOS Parallel Counter Using Pipeline Partitioning. International Journal of Engineering Research, 2(8), 491–495.
Search in Google Scholar Back to article
9. Bindu, S. A. (2015). Review on High Speed CMOS Counter Using Altera MAX300A. International Journal of Advanced Research in Computer and Communication Engineering, 4(12), 589–592.
Search in Google Scholar Back to article
10. Borysenko, O., Kalashnikov, V., Kalashnikova, N., & Matsenko, S. (2017). The Fibonacci Numeral System for Computer Vision, Computer Vision in Control Systems-3: Aerial and Satellite Image Processing. Springer International Publishing AG, 321–343.10.1007/978-3-319-67516-9_11
Search in Google Scholar Back to article
11. Azarov, O. (2015). The high-speed reversible Fibonacci counter. Information Technology and Computer Engineering, 1, 27–32.
Search in Google Scholar Back to article
12. Azarov, O. (2015). Method of quick decrement count with linear hardware increasing when orders are adding. Bulletin of the Vinnytsia Polytechnic Institute, 2(119), 57–61.
Search in Google Scholar Back to article
13. Azarov, O. (2014). Method of building the high-speed Fibonacci counters. Information and management problems, 2(46), 5–8.10.18372/2073-4751.2.7707
Search in Google Scholar Back to article
14. Useful Model Patent No. 89153U, MPК 14 N03K 23/00. (2014). Pulse counter, Borysenko, O., Matsenko S., applicant and patentholder Sumy State University, No. u201313302, declared: 15.11.2013, published: 10.04.2014.
Search in Google Scholar Back to article

Noise Immunity of the Fibonacci Counter with the Fractal Decoder Device for Telecommunication Systems

Abstract

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