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Design and analysis of a single-stage cascode LNA for S-band application in 180-nm CMOS technology Cover

Design and analysis of a single-stage cascode LNA for S-band application in 180-nm CMOS technology

Open Access
|Dec 2025

Abstract

This paper presents a high-gain, single-stage cascode low noise amplifier (LNA) tailored for S-band applications, implemented in a 180-nm CMOS process. The design employs a common-source cascode topology with inductive degeneration, enabling a careful trade-off between gain, noise figure, and input matching. Schematic simulations indicate a peak gain of 53.2 dB and a low noise figure of 1.51-1.74 dB across the S-band, with excellent impedance matching. The amplifier is unconditionally stable and occupies a compact core area of only 0.175 mm². Operating with a power consumption of 45 mW, these results demonstrate that the proposed LNA provides a competitive, area-efficient, and robust solution for modern S-band wireless systems, achieving performance levels comparable to more complex multi-stage architectures while maintaining simplicity and design efficiency. The design also achieves excellent reverse isolation (S12 < –48 dB), output matching (S22 = –12.75 dB), and unconditional stability (K > 1), further demonstrating the robustness of the proposed LNA.

DOI: https://doi.org/10.2478/jee-2025-0055 | Journal eISSN: 1339-309X | Journal ISSN: 1335-3632
Language: English
Page range: 533 - 539
Submitted on: Sep 15, 2025
Published on: Dec 6, 2025
Published by: Slovak University of Technology in Bratislava
In partnership with: Paradigm Publishing Services
Publication frequency: 6 issues per year

© 2025 Manish Kumar, Abhishek Sharma, Abhay Chaturvedi, Manish Gupta, Rajesh Kumar Singh, Jyotsna Ladkani, published by Slovak University of Technology in Bratislava
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.