Have a personal or library account? Click to login
Performance analysis of low-power multi-threshold CMOS-based 10T SRAM cell Cover

Performance analysis of low-power multi-threshold CMOS-based 10T SRAM cell

Open Access
|Jun 2025

References

  1. H. Sarkar and S. Kundu, “Standby Leakage Current Estimation Model for Multi-Threshold CMOS Inverter Circuit in Deep Submicron Technology,” 19th International Symposium on VLSI Design and Test, pp. 1-6, 2017.
  2. J. B. Kim and D.W. Kim, “Low-Power Carry Look-Ahead Adder with Multi-Threshold Voltage CMOS Technology,” International Semiconductor Conference, pp. 537-540, 2007.
  3. R. Bhaskar, R. Dheeraj, S. Saravanan, and K. Jagannadha Naidu, “A Low Power and High Speed 10 Transistor Full Adder Using Multi-Threshold Technique,” International Conference on Industrial and Information Systems, pp. 371-374, 2016.
  4. K. Gupta, N. Pandey, and M. Gupta, “Low Power Multi-Threshold MOS Current Mode Logic Asynchronous Pipeline Circuits,” International Conference on Power Electronics, pp. 1-4, 2012.
  5. S. Qureshi and K. R. Sanjeev, “Power and Performance Optimization Using Multi-Voltage, Multi-Threshold and Clock Gating for Low-End Microprocessors,” TENCON IEEE Region 10 Conference, pp. 1-6, 2009.
  6. G. Ahmad, Y. Kumar, and P. K. Sahu, “High Performance Multi-Threshold Voltage Level Converter for Multi-VDD Systems,” Students Conference on Engineering and Systems, pp. 1-4, 2013.
  7. S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, and J. Yamada, “1V High-Speed Digital Circuit Technology With 0.5/spl mu/m Multi-Threshold CMOS,” IEEE International ASIC Conference and Exhibit, pp. 186-189, 1993.
  8. S. H. Zadeh, T. Ytterdal, and S. Aunet, “Multi-threshold Voltage and Dynamic Body Biasing Techniques for Energy Efficient Ultra Low Voltage Subthreshold Adders,” IEEE Nordic Circuits and Systems Conference, pp. 1-6, 2020.
  9. M. Deepak and V. K. Tomar, “Performance Evaluation of 6T, 7T, 8T, and 9T SRAM cell Topologies at 90 nm Technology Node,” International Conference on Computing, Communication and Networking Technologies, pp. 16-201, 2020.
  10. H. V. Ravish, J. Fadnavis, and G. G. Spoorthi, “Memory Design and Verification of SRAM-Based Energy Efficient Ternary Content Addressable Memory,” International Conference on Information Systems and Computer Networks, pp. 90-104, 2021.
  11. S. Anusha et al., “MTCMOS 8T SRAM Cell with Improved Stability and Reduced Power Consumption,” International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics, pp. 176-803, 2021.
  12. M. G. Ganavi and B. S. Premananda, “Design of Low-Power Square Root Carry Select Adder and Wallace Tree Multiplier using Adiabatic Logic,” Springer Lecture Notes in Electrical Engineering, vol. 545, pp. 767-781, 2018.
  13. B. S. Premananda and S. Sreedhar, “Low-Power Phase Frequency Detector Using Hybrid AVLS and LECTOR Techniques for Low-Power PLL,” Advances in Electrical and Electronic Engineering, vol. 20, no. 3, pp. 294-303, 2022.
  14. U. Prashant, R. Mehra, and N. Thakur, “Low-power Design of an SRAM cell for Portable Devices,” International Conference on Computer and Communication Technology, pp. 255-259, 2010.
  15. P. B. Siddaiah, S. Valivati, and A. Rehman, “TSPC-AVLS Based Low-Power 16/17 Dual Modulus Prescaler Design,” IETE Journal of Research, vol. 70, no. 4, pp. 4149-4158, 2024.
  16. Lin, Sheng, Yong-Bin Kim, and F. Lombardi, “A Low Leakage 9T SRAM Cell for Ultra Low Power Operation,” 18th ACM Great Lakes symposium on VLSI, pp. 123-126, 2008.
  17. K. Navneet, N. Gupta, H. Pahuja, B. Singh, and S. Panday, “Low-power FINFET Based 10T SRAM Cell,” International Innovative Applications of Computational Intelligence on Power, Energy and Controls with their Impact on Humanity, pp. 227-233, 2016.
  18. P. B. Siddaiah, A. Rehman, and P. Megha, “Area and Power Efficient AVLS-TSPC-Based Diffused Bit Generator for Key Generation,” Springer Circuits, Systems, and Signal Processing, vol. 43, pp. 3103-3117, 2024.
  19. A. Bhaskar, “Design and Analysis of Low-power SRAM Cells,” Innovations in Power and Advanced Computing Technologies, pp. 1-5, 2017.
  20. A. Bajpai, A. R. Anurag, G. Shakthivel, and P. B. Siddaiah, “Design of Low-power and High-speed 16-bit Square Root Carry Select Adder using AL,” IEEE International Conference on Circuits, Control, Communication and Computing, pp. 1-4, 2018.
DOI: https://doi.org/10.2478/jee-2025-0030 | Journal eISSN: 1339-309X | Journal ISSN: 1335-3632
Language: English
Page range: 300 - 306
Submitted on: Apr 2, 2025
|
Published on: Jun 19, 2025
In partnership with: Paradigm Publishing Services
Publication frequency: 6 issues per year

© 2025 Premananda B. Siddaiah, Vallamkonda Ch. Dheeraj, published by Slovak University of Technology in Bratislava
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.