Abstract
Static Random-Access Memory (SRAM) used in cache memories faces significant power challenges due to increased leakage power. To minimize the overall power dissipation of memory units, SRAM cells should be designed to consume less power. The design of a low-power SRAM cell is proposed, utilizing the multi-threshold CMOS (MTCMOS) technique. The work builds upon, identifying a gap in the literature related to efficient power management in SRAM cells. The methodology employed in this work involves integrating the MTCMOS technique into the SRAM cells. Power gating is implemented by adding control signals and transistors to selectively activate or deactivate the power supply to the SRAM cells during idle states. The proposed cell is implemented using the Cadence Virtuoso tool, utilizing the GPDK 45nm technology library. The simulation results were analyzed using Cadence Spectre. The power analysis performed with Spectre shows a significant power reduction of 78.54% and 28.86% for the MTCMOS-based 10T SRAM cells when compared to both 6T SRAM and existing MTCMOS-based 8T SRAM cells, respectively. Power consumption during sleep time is effectively minimized, improving power efficiency and stability. The results are quantified and analyzed, highlighting the performance benefits of the proposed SRAM cell for low-power designs.