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A Methodology for the Synthesis and Evaluation of Hardware Accelerators Cover

A Methodology for the Synthesis and Evaluation of Hardware Accelerators

Bulletin of the Polytechnic Institute of Iași. Electrical Engineering, Power Engineering, Electronics Section
Volume 69 (2023): Issue 2 (June 2023)
By: Cristian-Tiberius Axinte  
Open Access
|Aug 2024

Authors

Cristian-Tiberius Axinte

cristian-tiberius.axinte@academic.tuiasi.ro

“Gheorghe Asachi” Technical University of Iaşi, Computer Engineering Department
DOI: https://doi.org/10.2478/bipie-2023-0011 | Journal eISSN: 2537-2726 | Journal ISSN: 1223-8139
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Language: English
Page range: 91 - 100
Submitted on: Jun 17, 2024
Accepted on: Jul 25, 2024
Published on: Aug 30, 2024
Published by: Gheorghe Asachi Technical University of Iasi
In partnership with: Paradigm Publishing Services
Publication frequency: 4 issues per year
Keywords:
Design Space Exploration (DSE),
High-Level Synthesis (HLS),
Domain-Specific Accelerator,
Power performance area (PPA) analysis,
RISC-V
Related subjects:
Engineering,
Electrical engineering,
Fundamentals of electrical engineering,
Automation,
Electronics,
Energy engineering

© 2024 Cristian-Tiberius Axinte, published by Gheorghe Asachi Technical University of Iasi
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.

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