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Figure 17.
COMPARISON BETWEEN DESIGN II & DESIGN III_
| Design Solutions # | Delay (gate delay) | % Optimization | Area (# of gates) | % Optimization |
|---|---|---|---|---|
| Solution I: using KSA Adder. | 23 | +15% | 6130 | |
| Solution II: using Comparator unit. | 27 | 3712 | +50% |
RADIX-8 BOOTH ENCODING_
| Inputs (bits of M-bit multiplier) | Partial Product | |||
|---|---|---|---|---|
| xi+2 | xi+1 | xi | xi−1 | PPRi |
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 1 | A |
| 0 | 0 | 1 | 0 | A |
| 0 | 0 | 1 | 1 | 2A |
| 0 | 1 | 0 | 0 | 2A |
| 0 | 1 | 0 | 1 | 3A |
| 0 | 1 | 1 | 0 | 3A |
| 0 | 1 | 1 | 1 | 4A |
| 1 | 0 | 0 | 0 | -4A |
| 1 | 0 | 0 | 1 | -3A |
| 1 | 0 | 1 | 0 | -3A |
| 1 | 0 | 1 | 1 | -2A |
| 1 | 1 | 0 | 0 | -2A |
| 1 | 1 | 0 | 1 | -A |
| 1 | 1 | 1 | 0 | -A |
| 1 | 1 | 1 | 1 | 0 |