Reducing the Phase-Noise In ΔΣ Fractional-N Synthezis – A Simulink Model

Emil Teodoru

doi:10.1515/kbo-2017-0166

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Reducing the Phase-Noise In ΔΣ Fractional-N Synthezis – A Simulink Model

International conference KNOWLEDGE-BASED ORGANIZATION

Volume 23 (2017): Issue 3 (June 2017)

By: Emil Teodoru

Open Access

|Jul 2017

Abstract

The resolution in fractional-N synthesis results as a fractional part of the reference frequency. This category of synthesizers permits a greater f_ref and a smaller N, a larger loop bandwidth, faster lock times and reduced output phase-noise. In ΔΣ fractional-N PLL’s the main problem is the specific quantization noise. To reduce them many techniques are used. The paper presents a Simulink model of the influence of the requantisation in the phase-noise cancellation process.

References

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Articles in this issue

DOI: https://doi.org/10.1515/kbo-2017-0166 | Journal eISSN: 2451-3113 | Journal ISSN: 1843-6722

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Language: English

Page range: 131 - 134

Published on: Jul 22, 2017

Published by: Nicolae Balcescu Land Forces Academy

In partnership with: Paradigm Publishing Services

Publication frequency: 3 issues per year

Keywords:

frequency synthesis,

ΔΣ modulator,

phase-noise

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Introductions and overviews,

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© 2017 Emil Teodoru, published by Nicolae Balcescu Land Forces Academy
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.

Volume 23 (2017): Issue 3 (June 2017)