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Reducing the Phase-Noise In ΔΣ Fractional-N Synthezis – A Simulink Model Cover

Reducing the Phase-Noise In ΔΣ Fractional-N Synthezis – A Simulink Model

By: Emil Teodoru  
Open Access
|Jul 2017

References

  1. [1] I. Galton, Delta-Sigma Data Conversion in Wireless Transceivers, Journal of Manufacturing Systems, IEEE Trans. on microwave theory and technique, vol.50, no. 1, January 2002, pp.302-315.10.1109/22.981283
  2. [2] Shu,K., Sanchez-Sinencio, E., CMOS PLL Synthesizers: Analysis and Design, Springer Science + Business Media, Inc., Boston, 2005, pp.69-101.
  3. [3] Egan, W.F., Frequency synthesis by phase lock, John Wiley & Sons, New York, 2000, pp.376.
  4. [4] Bertran Bakkaloglu, Sayfe Kiaei, Bikram Chaudhuri, Delta-Sigma (Δ-Σ) frequency synthesizers for wireless applications, Computers Standard & Interfaces, volume 29, Issue 1, January 2007, pp. 19-30.10.1016/j.csi.2005.12.003
  5. [5] Sudhakar Pamarti, Ian Galton, Phase-Noise Cancellation Design Tradeoffs in Delta - Sigma Fractional-N PLL-s, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol.50, no.11, November 2003, pp. 829-838.10.1109/TCSII.2003.819117
Language: English
Page range: 131 - 134
Published on: Jul 22, 2017
Published by: Nicolae Balcescu Land Forces Academy
In partnership with: Paradigm Publishing Services
Publication frequency: 3 issues per year

© 2017 Emil Teodoru, published by Nicolae Balcescu Land Forces Academy
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.