A simple reconfigurable microprocessor in a 36 macrocell CPLD

This paper describes a simple microprocessor developed using a complex programmable logic device (CPLD), with an instruction set optimized for data acquisition applications. The processor encompasses a tiny instruction set having only the instructions required in data acquisition applications. Due to optimization of the features, it was possible to fit both the CPU and the programme memory in the 36 macrocell Xilinx XC9536XL CPLD. The designing of the CPU was carried out using the hardware description language VHDL. The reconfigurability of the CPLD using VHDL enables the change of features of the CPU, including the instruction set, to suit user requirements. An example data acquisition system implemented using this CPU is also discussed.

Keywords: CPLD, data acquisition, FPGA, microcontrollers, reconfigurable computing, VHDL.

Doi: 10.4038/jnsfsr.v39i3.3630

J.Natn.Sci.Foundation Sri Lanka 2011 39 (3): 261-266