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Improving the LUT Count for Mealy FSMS with Transformation of Output Collections Cover

Improving the LUT Count for Mealy FSMS with Transformation of Output Collections

International Journal of Applied Mathematics and Computer Science
Volume 32 (2022): Issue 3 (September 2022)
By: Alexander Barkalov,  Larysa Titarenko and  Małgorzata Mazurkiewicz  
Open Access
|Oct 2022

Authors

Alexander Barkalov

a.barkalov@imei.uz.zgora.pl

Institute of Metrology, Electronics and Computer Science, University of Zielona Góra, Zielona Góra, Poland

Larysa Titarenko

l.titarenko@imei.uz.zgora.pl

Institute of Metrology, Electronics and Computer Science, University of Zielona Góra, Zielona Góra, Poland

Małgorzata Mazurkiewicz

m.mazurkiewicz@issi.uz.zgora.pl

Institute of Control and Computation Engineering, University of Zielona Góra, Zielona Góra, Poland
DOI: https://doi.org/10.34768/amcs-2022-0035 | Journal eISSN: 2083-8492 | Journal ISSN: 1641-876X
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Language: English
Page range: 479 - 494
Submitted on: Dec 9, 2021
|
Accepted on: Mar 23, 2022
|
Published on: Oct 8, 2022
Published by: University of Zielona Góra
In partnership with: Paradigm Publishing Services
Publication frequency: 4 issues per year
Keywords:
Mealy FSM,
FPGA,
LUT,
synthesis,
state codes
Related subjects:
Mathematics,
Applied mathematics

© 2022 Alexander Barkalov, Larysa Titarenko, Małgorzata Mazurkiewicz, published by University of Zielona Góra
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 3.0 License.

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