References
- MAHONEY, M.: DSP-Based Testing of Analog and Mixed-Signal Circuits, IEEE Computer Society Press, Los Alamitos, 1987
- HUERTAS, J. L.: Test and Design-for-Testability in Mixed-Signal Integrated Circuits, Kluwer Academic Publishers, Dordrecht, 2004.10.1007/978-0-387-23521-9
- DALLET, D.—MACHADO DA SILVA, M.: Dynamic Characterisation of Analogue-to-Digital Converters, Springer, 2005.
- DOERNBERG, J.—LEE, H. S.—HODGES, D. A.: Full-Speed Testing of A/D Converters, IEEE Journal of Solid State Circuits 19 No. 6 (1984), 820-827.10.1109/JSSC.1984.1052232
- VANDEN BOSSCHE, M.—SCHOUKENS, J.—RENNEBOOG, J.: Dynamic Testing and Diagnostics of A/D Converters, IEEE Transactions on Circuits and Systems 33 No. 8 (1986), 775-785.10.1109/TCS.1986.1086004
- WAGDY, M. F.—AWAD, S. S.: Determining ADC Effective Number of Bits via Histogram Testing, IEEE Transactions on Instrumentation and Measurement 40 No. 4 (1991), 770-772.10.1109/19.85350
- CARBONE, P.—CHIORBOLI, G.: ADC Sinewave Histogram Testing with Quasi-Coherent Sampling, IEEE Transactions on Instrumentation and Measurement 50 No. 4 (2001), 949-953.10.1109/19.948305
- BLAIR, J.: Histogram Measurement of ADC Nonlinearities using Sine waves, IEEE Transactions on Instrumentation and Measurement 43 No. 3 (1994), 373-383.10.1109/19.293454
- ALEGRIA, F. C.—SERRA, A. C.: Error in the Estimation of Transition Voltages with the Standard Histogram Test of ADCs, Measurement 35 No. 4 (2004), 389-397.
- ALEGRIA, F. C.—SERRA, A. C.: Overdrive in the Standard Histogram Test of ADCs, Measurement 35 No. 4 (2004), 381-387.
- ALEGRIA, F. C.—SERRA, A. C.: Standard Histogram Test Precision of ADC Gain and Offset Error Estimation, IEEE Transactions on Instrumentation and Measurement 56 No. 5 (2007), 1527-1531.10.1109/TIM.2007.907978
- HSIN-WEN, T.—BIN-DA, L.—SOON-JYH, C.: Histogram Based Testing Strategy for ADC, Proc. 15th Asian Test Symposium, 2006, pp. 51-54.
- ALEGRIA, F. C.—ARPAIA, P.—DAPONTE, P.—SERRA, A. C.: An ADC Histogram Test based on Small-AmplitudeWaves, Measurement 31 No. 4 (2002), 271-279.
- SERRA, A. C.—ALEGRIA, F.—MARTINS, R.—DA SILVA, M. F.: Analog-to-Digital Converter Testing - New Proposals, Computer Standards & Interfaces 26 No. 1 (2004), 3-13.10.1016/S0920-5489(03)00057-6
- RENOVELL, M.—AZAIS, F.—BERNARD, S.—BERTRAND, Y.: Hardware Resource Minimization for a Histogram-Based ADC BIST, Proc. 18th IEEE VLSI Test Symposium, 2000, pp. 247-252.
- AZAIS, F.—BERNARD, S.—BETRAND, Y.—RENOVELL, M.: Towards an ADC BIST Scheme using the Histogram Test Technique, Proc. IEEE European Test Workshop, 2000, pp. 53-58.
- AZAIS, F.—BERNARD, S.—BERTRAND, Y.—RENOVELL, M.: Implementation of Linear Histogram BIST for ADCs, Proc. DATE 2001, 2001, pp. 590-595.
- ROBERTS, G. W.—LU, A. K.: Analog Signal Generation for Built-in Self-Test of Mixed Signal Integrated Circuits, Kluwer Academic Publishers, Norwell, 1995.10.1007/978-1-4615-2341-3
- YONG-SHENG, W.—JIN-XIANG, W.—FENG-CHANG, L.— YI-ZHENG, Y.: Optimal Schemes for ADC BIST Based on Histogram, Proc. 14th Asian Test Symposium, 2005, pp. 52-57.10.1109/ATS.2005.86
- BRAGA, J. A.—MACHADO DA SILVA, J.—ALVES, J. C.— MATOS, J. S.: A Wrapper for Testing Analogue to Digital Converters Cores in SoCs, Proc. 9th IEEE European Test Symposium, 2004), pp. 170-175.
- http://grouper.ieee.org/groups/1500/
- KAC, U.—NOVAK, F.—AZAIS, F.—NOUET, P.—RENOVELL, M.: Extending IEEE Std. 1149.4 Analog Boundary Modules to Enhance Mixed-Signal Test, IEEE Design & Test of Computers 20 No. 2 (2003), 32-39.10.1109/MDT.2003.1188260
- NOVAK, F.—MRAK, P.—BIASIZZO, A.: Test Strategies for Embedded ADC Cores in a System-on-Chip, a Case Study, Computing and Informatics, (accepted for publication).