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A Resource-Efficient 4-Qubit Circuit for Bit-Flip Error Correction Using Feynman Gates Cover

A Resource-Efficient 4-Qubit Circuit for Bit-Flip Error Correction Using Feynman Gates

Open Access
|Aug 2025

Figures & Tables

Figure 1.

Gate-Level Diagram—Part 1 of the Proposed Error Correction Circuit (Correction of q[2] and q[1]).

Figure 2.

Gate-Level Diagram—Part 2 of the Proposed Circuit (Verification and Adjustment of q[0]).

Figure 3.

Gate-Level Diagram—Part 3 of the Proposed Circuit (Final Correction Based on Auxiliary State).

Figure 4.

Repeated Subcircuit Block (Used in All Three Parts of the Circuit).

Figure 5.

Block Diagram of the Full 4-Qubit Bit-Flip Error Correction Architecture.

Matrix representation of a 3-qubit layout result_

11101000
00000000
00000000
00000000
00000000
00000000
00000000
00010111

Substructure-Block Truth Table_

Column1Column2Column3
RowInput StateOutput State
R100001000
R200010001
R300100010
R400110011
R501000100
R601010101
R701100110
R801111111
R910000000
R1010011001
R1110101010
R1210111011
R1311001100
R1411011101
R1511101110
R1611110111

Substructure-Block Unitary Matrix_

0000000010000000
0100000000000000
0010000000000000
0001000000000000
0000100000000000
0000010000000000
0000001000000000
0000000000000001
1000000000000000
0000000001000000
0000000000100000
0000000000010000
0000000000001000
0000000000000100
0000000000000010
0000000100000000

Simulation results showing fidelity comparison across all test cases_

Error StateTarget StateDetection AccuracyCorrection Fidelity
|001〉|000〉100%100%
|010〉|000〉100%100%
|100〉|000〉100%100%
|110〉|111〉100%100%
|101〉|111〉100%100%
|011〉|111〉100%100%
|111〉|111〉100%100%
|000〉|000〉100%100%

Matrix representation of a 3-qubit layout process_

(000|000)(000|000)(000|000)(000|111)(000|000)(000|111)(000|111)(000|111)
(001|000)(001|000)(001|000)(001|111)(001|000)(001|111)(001|111)(001|111)
(010|000)(010|000)(010|000)(010|111)(010|000)(010|111)(010|111)(010|111)
(011|000)(011|000)(011|000)(011|111)(011|000)(011|111)(011|111)(011|111)
(100|000)(100|000)(100|000)(100|111)(100|000)(100|111)(100|111)(100|111)
(101|000)(101|000)(101|000)(101|111)(101|000)(101|111)(101|111)(101|111)
(110|000)(110|000)(110|000)(110|111)(110|000)(110|111)(110|111)(110|111)
(111|000)(111|000)(111|000)(111|111)(111|000)(111|111)(111|111)(111|111)

Comparison of Error-Correcting Circuit Approaches_

FeatureProposed CircuitShor Code (9-Qubit)Steane Code (7-Qubit)
Total Qubits Required497
Correctable Error TypesBit-flipBit + PhaseBit + Phase
Ancilla Qubits Used1≥3≥2
Gate Types UsedCNOT, NOTCNOT, H, S, TCNOT, H, S, T
Circuit Depth (approx.)LowHighHigh
Implementation ComplexityLowHighHigh
Detection Accuracy (simulated)100%100% (theoretical)100% (theoretical)
Fidelity (ideal simulation)100%100%100%
Simulation Tool UsedIBM ComposerTheoreticalTheoretical

Truth table of the intended operation_

Column1Column2Column3
Input StateExpected Output State
0|000>|000>
1|001>|000>
2|010>|000>
3|011>|111>
4|100>|000>
5|101>|111>
6|110>|111>
7|111>|111>
DOI: https://doi.org/10.2478/qic-2025-0019 | Journal eISSN: 3106-0544 | Journal ISSN: 1533-7146
Language: English
Page range: 344 - 355
Submitted on: May 13, 2025
Accepted on: Jun 27, 2025
Published on: Aug 22, 2025
In partnership with: Paradigm Publishing Services
Publication frequency: 1 issue per year

© 2025 Dimitrios Gryllakis, Kyriakos N. Sgarbas, published by Cerebration Science Publishing Co., Limited
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.