Figure 1.
![Gate-Level Diagram—Part 1 of the Proposed Error Correction Circuit (Correction of q[2] and q[1]).](https://sciendo-parsed.s3.eu-central-1.amazonaws.com/68a877c8afc50a4de0964e8a/j_qic-2025-0019_fig_001.jpg?X-Amz-Algorithm=AWS4-HMAC-SHA256&X-Amz-Content-Sha256=UNSIGNED-PAYLOAD&X-Amz-Credential=ASIA6AP2G7AKO6OGLGK3%2F20260323%2Feu-central-1%2Fs3%2Faws4_request&X-Amz-Date=20260323T015705Z&X-Amz-Expires=3600&X-Amz-Security-Token=IQoJb3JpZ2luX2VjEKf%2F%2F%2F%2F%2F%2F%2F%2F%2F%2FwEaDGV1LWNlbnRyYWwtMSJIMEYCIQCqSnDvC97vv76HiPeV5HZCBc3KSW2z5VIixoUMwOXW4gIhANM2rlh2RH1VWghl994NYPvvnaIAKPKrarZYwC1BWggIKrwFCHAQAhoMOTYzMTM0Mjg5OTQwIgwAITpqVWXUwVvvcuQqmQVWT9DUI0GwsuW8MG1L0eNmjbUvt9%2F9toDDn0UWyRWn1NzC%2BnSkOWMATTeZZ8cLhZi2fksIvFhEh%2Fz6PWHzP%2B8XVdsVsgCbgUVFAG5zBOYS3cvEYxXehvft1%2FGn1H%2F9yN1zYbuClwpbsaOkbg3oEtXTk4CCwlj2upBrFwNnBM2zRLJP5CUb03mzWnPGKwvtY5ZDdPfoykWFWr%2BS5F3wSGUhcCgvYBKbhD%2F%2FH%2BepL7N6jbbsoOm1fmnO1g6kE5c0Xs%2BMe9Ekb%2FG%2FRffzNYE3umIU%2BROPx8yQ16SR0J%2BZBK%2FbeHO6yHt2tO94bBlbTzcak4mQtsngr8bqyPQvEEUOcsLi60k1ukrIewhfigTwTOaeuJ0EltDS9BOGi6TDmMtON7kGLYVBcifnT84psu%2BqvZnFMe8JND0P56snkcZQFksm5GO72h4kpxnOqHRgnK%2BXilP8f3Fu4ZlVLC20mR7Kk8D8RoRfAMqgZ%2BVyN0VTTjDaZQD5QLNyYE3622tU9x5OLZjUq1UQ1jz0tURw%2FpoAbN9YHjGdXZs8NYzYvkQlPhPrzEJV7gbM762KxURjr5rsJKqdI%2FhdCEaYk3Vi0ePHtdzo6cGzaVyzxZISZMXTqFkDCsVT0MYgi4GqeSkNtGM3IpwXOeaWEYSIlbZVfDWhJvnMUZOFtYHBfpfjQ2%2F9FGgTh5W5HN%2Fi7E4j9%2FnVYqYlzCogUYZGY7iRbkUsbrW%2BqyjyxMHG7R%2BjtEkhrJs0S3t9OJRz68vdflh3cFSUlofzlsb9QXgZg0FDdcPqUH8XQQ%2F1ecIMz0MOQH8LWwT%2B5BzrWSnfK3zU60aSctaD6cS5DcpJKZQFYi0QAnWLnIi2m1S7jFqvSF7%2FPWh07BfNtf79TjV6pgxL%2BpImUzDI8oHOBjqwAV6n5VmmE9gfEYxre9%2BaEwABovps6qHVLm2XXq8y1vqoef3I61uJIs3%2ByzctFPfwSMQmG0FsSx%2F4mp7a3ycsQxHse8AgZJwljFz7OWq1Iooz5owdq6I5a%2BLNG%2BrA3SC5vBYW%2FD6e4ye0ERQIYwBXHLrLrXaEy4wRUEoKjJXXFlhJvvthpL7ZLMG69e%2B9jE6h%2FTYWo6yadDWfwIptyp6aeZCErBlTa37K7jW1BwNAmAh1&X-Amz-Signature=1921c2ce825cfcc11fb2921955a14b32230ec0866515f75fa6c177fec5f58747&X-Amz-SignedHeaders=host&x-amz-checksum-mode=ENABLED&x-id=GetObject)
Figure 2.
![Gate-Level Diagram—Part 2 of the Proposed Circuit (Verification and Adjustment of q[0]).](https://sciendo-parsed.s3.eu-central-1.amazonaws.com/68a877c8afc50a4de0964e8a/j_qic-2025-0019_fig_002.jpg?X-Amz-Algorithm=AWS4-HMAC-SHA256&X-Amz-Content-Sha256=UNSIGNED-PAYLOAD&X-Amz-Credential=ASIA6AP2G7AKO6OGLGK3%2F20260323%2Feu-central-1%2Fs3%2Faws4_request&X-Amz-Date=20260323T015705Z&X-Amz-Expires=3600&X-Amz-Security-Token=IQoJb3JpZ2luX2VjEKf%2F%2F%2F%2F%2F%2F%2F%2F%2F%2FwEaDGV1LWNlbnRyYWwtMSJIMEYCIQCqSnDvC97vv76HiPeV5HZCBc3KSW2z5VIixoUMwOXW4gIhANM2rlh2RH1VWghl994NYPvvnaIAKPKrarZYwC1BWggIKrwFCHAQAhoMOTYzMTM0Mjg5OTQwIgwAITpqVWXUwVvvcuQqmQVWT9DUI0GwsuW8MG1L0eNmjbUvt9%2F9toDDn0UWyRWn1NzC%2BnSkOWMATTeZZ8cLhZi2fksIvFhEh%2Fz6PWHzP%2B8XVdsVsgCbgUVFAG5zBOYS3cvEYxXehvft1%2FGn1H%2F9yN1zYbuClwpbsaOkbg3oEtXTk4CCwlj2upBrFwNnBM2zRLJP5CUb03mzWnPGKwvtY5ZDdPfoykWFWr%2BS5F3wSGUhcCgvYBKbhD%2F%2FH%2BepL7N6jbbsoOm1fmnO1g6kE5c0Xs%2BMe9Ekb%2FG%2FRffzNYE3umIU%2BROPx8yQ16SR0J%2BZBK%2FbeHO6yHt2tO94bBlbTzcak4mQtsngr8bqyPQvEEUOcsLi60k1ukrIewhfigTwTOaeuJ0EltDS9BOGi6TDmMtON7kGLYVBcifnT84psu%2BqvZnFMe8JND0P56snkcZQFksm5GO72h4kpxnOqHRgnK%2BXilP8f3Fu4ZlVLC20mR7Kk8D8RoRfAMqgZ%2BVyN0VTTjDaZQD5QLNyYE3622tU9x5OLZjUq1UQ1jz0tURw%2FpoAbN9YHjGdXZs8NYzYvkQlPhPrzEJV7gbM762KxURjr5rsJKqdI%2FhdCEaYk3Vi0ePHtdzo6cGzaVyzxZISZMXTqFkDCsVT0MYgi4GqeSkNtGM3IpwXOeaWEYSIlbZVfDWhJvnMUZOFtYHBfpfjQ2%2F9FGgTh5W5HN%2Fi7E4j9%2FnVYqYlzCogUYZGY7iRbkUsbrW%2BqyjyxMHG7R%2BjtEkhrJs0S3t9OJRz68vdflh3cFSUlofzlsb9QXgZg0FDdcPqUH8XQQ%2F1ecIMz0MOQH8LWwT%2B5BzrWSnfK3zU60aSctaD6cS5DcpJKZQFYi0QAnWLnIi2m1S7jFqvSF7%2FPWh07BfNtf79TjV6pgxL%2BpImUzDI8oHOBjqwAV6n5VmmE9gfEYxre9%2BaEwABovps6qHVLm2XXq8y1vqoef3I61uJIs3%2ByzctFPfwSMQmG0FsSx%2F4mp7a3ycsQxHse8AgZJwljFz7OWq1Iooz5owdq6I5a%2BLNG%2BrA3SC5vBYW%2FD6e4ye0ERQIYwBXHLrLrXaEy4wRUEoKjJXXFlhJvvthpL7ZLMG69e%2B9jE6h%2FTYWo6yadDWfwIptyp6aeZCErBlTa37K7jW1BwNAmAh1&X-Amz-Signature=6bd45626112970f137136954cf16c78596a55f4bb2a0c5c1baa4c1f974ac206a&X-Amz-SignedHeaders=host&x-amz-checksum-mode=ENABLED&x-id=GetObject)
Figure 3.

Figure 4.

Figure 5.

Matrix representation of a 3-qubit layout result_
| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 |
Substructure-Block Truth Table_
| Column1 | Column2 | Column3 |
|---|---|---|
| Row | Input State | Output State |
| R1 | 0000 | 1000 |
| R2 | 0001 | 0001 |
| R3 | 0010 | 0010 |
| R4 | 0011 | 0011 |
| R5 | 0100 | 0100 |
| R6 | 0101 | 0101 |
| R7 | 0110 | 0110 |
| R8 | 0111 | 1111 |
| R9 | 1000 | 0000 |
| R10 | 1001 | 1001 |
| R11 | 1010 | 1010 |
| R12 | 1011 | 1011 |
| R13 | 1100 | 1100 |
| R14 | 1101 | 1101 |
| R15 | 1110 | 1110 |
| R16 | 1111 | 0111 |
Substructure-Block Unitary Matrix_
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Simulation results showing fidelity comparison across all test cases_
| Error State | Target State | Detection Accuracy | Correction Fidelity |
|---|---|---|---|
| |001〉 | |000〉 | 100% | 100% |
| |010〉 | |000〉 | 100% | 100% |
| |100〉 | |000〉 | 100% | 100% |
| |110〉 | |111〉 | 100% | 100% |
| |101〉 | |111〉 | 100% | 100% |
| |011〉 | |111〉 | 100% | 100% |
| |111〉 | |111〉 | 100% | 100% |
| |000〉 | |000〉 | 100% | 100% |
Matrix representation of a 3-qubit layout process_
| (000|000) | (000|000) | (000|000) | (000|111) | (000|000) | (000|111) | (000|111) | (000|111) |
| (001|000) | (001|000) | (001|000) | (001|111) | (001|000) | (001|111) | (001|111) | (001|111) |
| (010|000) | (010|000) | (010|000) | (010|111) | (010|000) | (010|111) | (010|111) | (010|111) |
| (011|000) | (011|000) | (011|000) | (011|111) | (011|000) | (011|111) | (011|111) | (011|111) |
| (100|000) | (100|000) | (100|000) | (100|111) | (100|000) | (100|111) | (100|111) | (100|111) |
| (101|000) | (101|000) | (101|000) | (101|111) | (101|000) | (101|111) | (101|111) | (101|111) |
| (110|000) | (110|000) | (110|000) | (110|111) | (110|000) | (110|111) | (110|111) | (110|111) |
| (111|000) | (111|000) | (111|000) | (111|111) | (111|000) | (111|111) | (111|111) | (111|111) |
Comparison of Error-Correcting Circuit Approaches_
| Feature | Proposed Circuit | Shor Code (9-Qubit) | Steane Code (7-Qubit) |
|---|---|---|---|
| Total Qubits Required | 4 | 9 | 7 |
| Correctable Error Types | Bit-flip | Bit + Phase | Bit + Phase |
| Ancilla Qubits Used | 1 | ≥3 | ≥2 |
| Gate Types Used | CNOT, NOT | CNOT, H, S, T | CNOT, H, S, T |
| Circuit Depth (approx.) | Low | High | High |
| Implementation Complexity | Low | High | High |
| Detection Accuracy (simulated) | 100% | 100% (theoretical) | 100% (theoretical) |
| Fidelity (ideal simulation) | 100% | 100% | 100% |
| Simulation Tool Used | IBM Composer | Theoretical | Theoretical |
Truth table of the intended operation_
| Column1 | Column2 | Column3 |
|---|---|---|
| Input State | Expected Output State | |
| 0 | |000> | |000> |
| 1 | |001> | |000> |
| 2 | |010> | |000> |
| 3 | |011> | |111> |
| 4 | |100> | |000> |
| 5 | |101> | |111> |
| 6 | |110> | |111> |
| 7 | |111> | |111> |