Figure 1.
![Gate-Level Diagram—Part 1 of the Proposed Error Correction Circuit (Correction of q[2] and q[1]).](https://sciendo-parsed.s3.eu-central-1.amazonaws.com/68a877c8afc50a4de0964e8a/j_qic-2025-0019_fig_001.jpg?X-Amz-Algorithm=AWS4-HMAC-SHA256&X-Amz-Content-Sha256=UNSIGNED-PAYLOAD&X-Amz-Credential=ASIA6AP2G7AKB44KBXA4%2F20251212%2Feu-central-1%2Fs3%2Faws4_request&X-Amz-Date=20251212T162745Z&X-Amz-Expires=3600&X-Amz-Security-Token=IQoJb3JpZ2luX2VjED8aDGV1LWNlbnRyYWwtMSJHMEUCICHpT%2BYxZGOPGC1krzOibIDRJXtKDvGz9ryRYcwxSLD7AiEA8VNSrldGkzQp3Z%2Bxy52Wq%2FSlHYHuTUov6iqmWpo0riIqvQUICBACGgw5NjMxMzQyODk5NDAiDI4ZhyXMSo87fc%2FykyqaBQb39pHNKfqcGsDLU1kM3UlpoUp7bzVTILgkAu0q8JLUwpa8JNmzzwXLORCJAYCGtNlbU3j4FgjK%2FyVbYE1a%2By8Mdi7Mgxxi0oNmmDCT%2FcY%2BD3aSkEpFZf5xMBjvZ%2BHyRPCQQHE7niZgPovR3sBAXGqLJBqglKIqPt4j55IB496z3vzJu4gaoSwSTmfU0Xo%2BO693SqRnhgCKNAFxAtaxLOtr61l56pXAd5tMt8JAqeXhnZrMRmYPMUPiqMm3DsOI4eDlzGuGbB0NsVfF4QABhz2%2BXDZj4BF22XsQasNRuriJ1oIw3YaJXyjjs4YPIjQPhtFMhviLjAW9XAcB%2FDpZhRET54QXrCmKS9kgO%2B%2BFep%2BkXiSTf5v3gKTF7ZhwqODl1tvPtgNyXGLH1dCfqkm%2BmsqYXcu%2BKXVOR5KUSuiZ5KceE9oIKwAIpkXhGddalqbb2otLFjUXHm5%2BEBsNjje3rmIZ5s%2Baf1CK9UjeFjm8uEpof6SWqMyYDWzJa8vAFG61gZTykNoBE7XPEtlm5tXT7ZqZwXboB7Kswb6Ymr%2FlcrYLXbkLF%2BTFgp9avDSeempUEacX7e5ijal1UCaHFREot9mTJr1hYdn84pEnOsvPsZAI1LNQYwgAyNIiFRq7w%2B87nmGq%2B%2B8mkgKSt%2BSjuCG%2FPwt7R5B6vfvflVwuy%2FsdwOEHw96UJv7746DVg7%2FEtjeGU8g%2BH3BJAOf%2FR5EKOKjIck3fpjYwtg5DON2IZEjj7lqPE62NBdysr1QprNeGu27go7wK40Lwa3Y%2B3KIyn0sBwLHG61zxs4yoE3OwqO%2BlaYk%2FDd7hxR2fkQj49Lhzu%2FMovfR%2FZqbRfJ2ivZtOd7L4%2FmnUupudmbAjna6BR%2B3VUvwbZ2m45FIcNn1xIzDi3PDJBjqxAfwA%2F%2BFkYxbeWM6yGcYgdXPuy8qChKRrh7TyNy6b8ynEzeVrIS5qAP7TwY978WULX18bG2VQ55pwsqJAYPz7LZtqjnCF6hQlx9plWn6AKTTjyfY3I3WM3SgIAqijoEtxwEDceRYGIZD%2BRCc6lTMhCdrWSg7YAcuIvA6%2B8Q0OxSWB5ugZYKRXvKQ0uS7SvzkKwTUBkvjAL4NlXP7KUHPwaI4hGLKKqeaUiDPVrWBQBFaP3g%3D%3D&X-Amz-Signature=8af3ddc6d6d36aa44f51b91635afbb29c27e1763205e44089469b97b1419adec&X-Amz-SignedHeaders=host&x-amz-checksum-mode=ENABLED&x-id=GetObject)
Figure 2.
![Gate-Level Diagram—Part 2 of the Proposed Circuit (Verification and Adjustment of q[0]).](https://sciendo-parsed.s3.eu-central-1.amazonaws.com/68a877c8afc50a4de0964e8a/j_qic-2025-0019_fig_002.jpg?X-Amz-Algorithm=AWS4-HMAC-SHA256&X-Amz-Content-Sha256=UNSIGNED-PAYLOAD&X-Amz-Credential=ASIA6AP2G7AKB44KBXA4%2F20251212%2Feu-central-1%2Fs3%2Faws4_request&X-Amz-Date=20251212T162745Z&X-Amz-Expires=3600&X-Amz-Security-Token=IQoJb3JpZ2luX2VjED8aDGV1LWNlbnRyYWwtMSJHMEUCICHpT%2BYxZGOPGC1krzOibIDRJXtKDvGz9ryRYcwxSLD7AiEA8VNSrldGkzQp3Z%2Bxy52Wq%2FSlHYHuTUov6iqmWpo0riIqvQUICBACGgw5NjMxMzQyODk5NDAiDI4ZhyXMSo87fc%2FykyqaBQb39pHNKfqcGsDLU1kM3UlpoUp7bzVTILgkAu0q8JLUwpa8JNmzzwXLORCJAYCGtNlbU3j4FgjK%2FyVbYE1a%2By8Mdi7Mgxxi0oNmmDCT%2FcY%2BD3aSkEpFZf5xMBjvZ%2BHyRPCQQHE7niZgPovR3sBAXGqLJBqglKIqPt4j55IB496z3vzJu4gaoSwSTmfU0Xo%2BO693SqRnhgCKNAFxAtaxLOtr61l56pXAd5tMt8JAqeXhnZrMRmYPMUPiqMm3DsOI4eDlzGuGbB0NsVfF4QABhz2%2BXDZj4BF22XsQasNRuriJ1oIw3YaJXyjjs4YPIjQPhtFMhviLjAW9XAcB%2FDpZhRET54QXrCmKS9kgO%2B%2BFep%2BkXiSTf5v3gKTF7ZhwqODl1tvPtgNyXGLH1dCfqkm%2BmsqYXcu%2BKXVOR5KUSuiZ5KceE9oIKwAIpkXhGddalqbb2otLFjUXHm5%2BEBsNjje3rmIZ5s%2Baf1CK9UjeFjm8uEpof6SWqMyYDWzJa8vAFG61gZTykNoBE7XPEtlm5tXT7ZqZwXboB7Kswb6Ymr%2FlcrYLXbkLF%2BTFgp9avDSeempUEacX7e5ijal1UCaHFREot9mTJr1hYdn84pEnOsvPsZAI1LNQYwgAyNIiFRq7w%2B87nmGq%2B%2B8mkgKSt%2BSjuCG%2FPwt7R5B6vfvflVwuy%2FsdwOEHw96UJv7746DVg7%2FEtjeGU8g%2BH3BJAOf%2FR5EKOKjIck3fpjYwtg5DON2IZEjj7lqPE62NBdysr1QprNeGu27go7wK40Lwa3Y%2B3KIyn0sBwLHG61zxs4yoE3OwqO%2BlaYk%2FDd7hxR2fkQj49Lhzu%2FMovfR%2FZqbRfJ2ivZtOd7L4%2FmnUupudmbAjna6BR%2B3VUvwbZ2m45FIcNn1xIzDi3PDJBjqxAfwA%2F%2BFkYxbeWM6yGcYgdXPuy8qChKRrh7TyNy6b8ynEzeVrIS5qAP7TwY978WULX18bG2VQ55pwsqJAYPz7LZtqjnCF6hQlx9plWn6AKTTjyfY3I3WM3SgIAqijoEtxwEDceRYGIZD%2BRCc6lTMhCdrWSg7YAcuIvA6%2B8Q0OxSWB5ugZYKRXvKQ0uS7SvzkKwTUBkvjAL4NlXP7KUHPwaI4hGLKKqeaUiDPVrWBQBFaP3g%3D%3D&X-Amz-Signature=f1e3c868ab447b9211c31de39596bf80eaa79ee328497e78daa05b96cb473c66&X-Amz-SignedHeaders=host&x-amz-checksum-mode=ENABLED&x-id=GetObject)
Figure 3.

Figure 4.

Figure 5.

Matrix representation of a 3-qubit layout result_
| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 |
Substructure-Block Truth Table_
| Column1 | Column2 | Column3 |
|---|---|---|
| Row | Input State | Output State |
| R1 | 0000 | 1000 |
| R2 | 0001 | 0001 |
| R3 | 0010 | 0010 |
| R4 | 0011 | 0011 |
| R5 | 0100 | 0100 |
| R6 | 0101 | 0101 |
| R7 | 0110 | 0110 |
| R8 | 0111 | 1111 |
| R9 | 1000 | 0000 |
| R10 | 1001 | 1001 |
| R11 | 1010 | 1010 |
| R12 | 1011 | 1011 |
| R13 | 1100 | 1100 |
| R14 | 1101 | 1101 |
| R15 | 1110 | 1110 |
| R16 | 1111 | 0111 |
Substructure-Block Unitary Matrix_
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Simulation results showing fidelity comparison across all test cases_
| Error State | Target State | Detection Accuracy | Correction Fidelity |
|---|---|---|---|
| |001〉 | |000〉 | 100% | 100% |
| |010〉 | |000〉 | 100% | 100% |
| |100〉 | |000〉 | 100% | 100% |
| |110〉 | |111〉 | 100% | 100% |
| |101〉 | |111〉 | 100% | 100% |
| |011〉 | |111〉 | 100% | 100% |
| |111〉 | |111〉 | 100% | 100% |
| |000〉 | |000〉 | 100% | 100% |
Matrix representation of a 3-qubit layout process_
| (000|000) | (000|000) | (000|000) | (000|111) | (000|000) | (000|111) | (000|111) | (000|111) |
| (001|000) | (001|000) | (001|000) | (001|111) | (001|000) | (001|111) | (001|111) | (001|111) |
| (010|000) | (010|000) | (010|000) | (010|111) | (010|000) | (010|111) | (010|111) | (010|111) |
| (011|000) | (011|000) | (011|000) | (011|111) | (011|000) | (011|111) | (011|111) | (011|111) |
| (100|000) | (100|000) | (100|000) | (100|111) | (100|000) | (100|111) | (100|111) | (100|111) |
| (101|000) | (101|000) | (101|000) | (101|111) | (101|000) | (101|111) | (101|111) | (101|111) |
| (110|000) | (110|000) | (110|000) | (110|111) | (110|000) | (110|111) | (110|111) | (110|111) |
| (111|000) | (111|000) | (111|000) | (111|111) | (111|000) | (111|111) | (111|111) | (111|111) |
Comparison of Error-Correcting Circuit Approaches_
| Feature | Proposed Circuit | Shor Code (9-Qubit) | Steane Code (7-Qubit) |
|---|---|---|---|
| Total Qubits Required | 4 | 9 | 7 |
| Correctable Error Types | Bit-flip | Bit + Phase | Bit + Phase |
| Ancilla Qubits Used | 1 | ≥3 | ≥2 |
| Gate Types Used | CNOT, NOT | CNOT, H, S, T | CNOT, H, S, T |
| Circuit Depth (approx.) | Low | High | High |
| Implementation Complexity | Low | High | High |
| Detection Accuracy (simulated) | 100% | 100% (theoretical) | 100% (theoretical) |
| Fidelity (ideal simulation) | 100% | 100% | 100% |
| Simulation Tool Used | IBM Composer | Theoretical | Theoretical |
Truth table of the intended operation_
| Column1 | Column2 | Column3 |
|---|---|---|
| Input State | Expected Output State | |
| 0 | |000> | |000> |
| 1 | |001> | |000> |
| 2 | |010> | |000> |
| 3 | |011> | |111> |
| 4 | |100> | |000> |
| 5 | |101> | |111> |
| 6 | |110> | |111> |
| 7 | |111> | |111> |