Design and Development of Boost PFC Converter for Medium-Power High-Voltage Power Supply

Deepu E. Koshy; S. A. Kannan; T. K. Sindhu; M. P. Shreelakshmi

doi:10.2478/pead-2026-0027

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Design and Development of Boost PFC Converter for Medium-Power High-Voltage Power Supply

Power Electronics and Drives

Volume 11 (2026): Issue 1 (January 2026)

By: Deepu E. Koshy , S. A. Kannan , T. K. Sindhu and M. P. Shreelakshmi

Open Access

|Sep 2026

Figures & Tables

Block diagram of the HV power supply system for a DBD-based ESP–NTP system. DBD, dielectric barrier discharge; ESP, electrostatic precipitators; HV: high voltage; NTP, non-thermal plasma; PFC, power factor correction.

Table 1.

Design specification for boost PFC.

Parameters	Value	Parameters	Value
Input voltage	230V AC	Switching frequency	50 kHz
Boost output voltage	400V DC	PFC inductor	6.6 mH
Output power	900 W	Equivalent load resistance	177.78 Ω

[i] PFC, power factor correction.

PFC control block diagram. PFC, power factor correction.

Inner current control loop in boost PFC systems. PFC, power factor correction.

Closed-loop step responses of the inner current loop with different PI tuning methods. T_s: Settling time, OS: overshoot, T_r: rise time. PI, proportional integral.

Simplified equivalent circuit diagram of boost PFC based on average power. PFC, power factor correction.

Outer voltage control loop in boost PFC systems. PFC, power factor correction.

Closed-loop step responses of the outer voltage loop with different PI tuning methods. T_s: Settling time, OS: overshoot, T_r: rise time. PI, proportional integral.

Control architecture of boost PFC converter with dual-loop regulation. PFC, power factor correction; PI, proportional integral.

Table 2.

Qualitative comparative performance of inner current control strategies for boost PFC converters.

Performance parameter	PI	PR	HCC	DB	MPC	MFPC	SMC	Proposed PI

	Computational and implementation aspects
Computational burden (per cycle)	L	M	L	H	VH	M	M	L
Implementation complexity	L	M	L	H	VH	M	H	L
Parameter sensitivity	M	M	L	VH	H	L	VL	M
	Dynamic performance
Current transient response	S	F	VF	VF	VF	F	F	S
Phase error (grid frequency)	NZ	Z	NrZ	Z	NrZ	NrZ	Z	NrZ
	Steady-state performance
Steady-state current THD	>5%	<5%	<3%	<5%	<2%	<5%	<3%	<5%
Steady-state error	NZ	Z	NrZ	Z	NrZ	NrZ	Z	NrZ

[i] DB, deadbeat; F, fast; H, high; HCC, hysteresis current control; L, low; M, moderate; MFPC, model-free predictive control; MPC, model predictive control; NrZ, near zero; NZ, non-zero; PI, proportional integral; PR, proportional resonant; S, slow; SMC, sliding mode control; VF, very fast; VH, very high; Z, zero.

Table 3.

Experimental hardware specifications and statistical performance parameters of the compared control strategies.

Control strategy (references)	Rated power (W)	Vin/Vout (V)	Output capacitor (μF)	Switching frequency (kHz)	THD (%)	PF
PI: Okilly and Baek (2022)	2,000	220/400	950	100	5.5	0.9935
PR: Liu et al. (2013)	3,000	220/400	940	19.2	N.R	N.R
HCC: Shehata et al. (2023)	100	40/100	1,000	21	2.61	0.999
DB: Mattavelli et al. (2005)	400	230/400	330	50	N.R	N.R
MPC: Israr and Samuel (2025)	500	220/400	100	20	1.8	0.999
MFPC: Gu et al. (2021)	1,000	110/300	990	50	N.R	0.99
SMC: Mohanty and Panda (2016)	500	230/390	470	200	2.4	0.999
Proposed work (FDM-GART PI)	900	230/400	1,000	50	4.7	0.999

[i] N.R. = Not explicitly reported in the text.DB, deadbeat; FDM, frequency-differentiated modelling; GART, grid-aligned resonance tuning; HCC, hysteresis current control; MFPC, model-free predictive control; MPC, model predictive control; PF, power factor; PI, proportional integral; PR, proportional resonant; SMC, sliding mode control; THD, total harmonic distortion.

Bode analysis of the effect of R_eff on the inner current loop.

Bode analysis of inner current loop for capacitor variations.

Combined plot of THD and settling time versus output capacitance. THD, total harmonic distortion.

Table 4.

Simulation parameters.

Parameters	Value	Parameters	Value
Output capacitor	1,000 µF	Switch on-resistance	0.25 Ω
ESR of capacitor	0.1076 Ω	Forward resistance of diode	0.03 Ω
Resistance of the inductor	0.5 Ω	Diode cut-in voltage	1.05V

[i] ESR, equivalent series resistance.

(a) Steady-state operation of boost PFC under rated load conditions; (b) Zoomed-in waveform showing input current tracking input-voltage and output-voltage ripple; (c) THD of input current. PFC, power factor correction; THD, total harmonic distortion.

Load regulation performance of boost PFC converter. PFC, power factor correction.

Line regulation performance of boost PFC converter. PFC, power factor correction.

Experimental hardware setup of the 900 W boost PFC prototype. PFC, power factor correction.

Input voltage V_in (C1: 200V/div), input current I_in (C2: 10 A/div), output current I_o (C4: 1 A/div), output voltage V_o (C3: 100V/div). PF, power factor; THD, total harmonic distortion.

Load regulation performance of boost PFC converter. Input voltage V_in (C1: 200V/div), input current I_in (C2: 10 A/div), output current I_o (C4: 2 A/div), output voltage V_o (C3: 100V/div). PFC, power factor correction.

Line regulation performance of boost PFC converter. Input voltage V_in (C1: 200V/div), input current I_in (C2: 10 A/div), output current I_o (C4: 2 A/div), output voltage V_o (C3: 100V/div). PFC, power factor correction.

(a) Input-current waveforms before and after PFC activation. (b) THD measurement. PF, power factor; PFC, power factor correction; THD, total harmonic distortion.

Power loss distribution of the boost PFC converter. PFC, power factor correction.

Table 5.

Analytical loss models and derived current expressions for the PFC converter power-stage components.

Components	Loss model	Analytical expression	Derived current expressions used for loss calculation
Bridge rectifier	Conduction loss, P_L_,BR,cond	$2 (V_{F} \times I_{in, avg}) + 2 (r_{d} \times {I_{in, rms}}^{2})$	$I_{in, avg} = \frac{4 V_{o} I_{o}}{π V_{in, pk}}; I_{in, rms} = \frac{\sqrt{2} V_{o} I_{o}}{V_{i n, p k}}$
Inductor	Copper loss, P_L,L,cu	${I_{L, rms}}^{2} R_{D C, L}$	$I_{L, avg} = \frac{4 V_{o} I_{o}}{π V_{i n, p k}}; I_{L, rms} = \frac{\sqrt{2} V_{o} I_{o}}{V_{i n, p k}}$
Inductor	Core loss, P_L,L,core	$P_{v} \times V_{c}$
Switch (MOSFET)	Conduction loss, P_L,sw,cond	${I_{sw, rms}}^{2} R_{D s (o n)}$	$\begin{matrix} I_{sw, avg} = \frac{4 V_{o} I_{o}}{π V_{i n, p k}} - I_{o}; \\ I_{s w, r m s} = \frac{2 V_{o} I_{o}}{V_{i n, p k}} \sqrt{\frac{1}{2} - \frac{4 V_{i n, p k}}{2 π V_{o}}} \end{matrix}$
Switch (MOSFET)	Switching loss, P_L,sw,sl	$\frac{f_{s}}{2} V_{o} I_{L, avg} (t_{r} + t_{f})$
Diode	Conduction loss, P_L,D,cond	$(V_{F} \times I_{D, avg}) + (r_{d} \times {I_{D, rms}}^{2})$	$I_{D, avg} = I_{o}; I_{D, rms} = 4 I_{o} \sqrt{\frac{V_{o}}{3 π V_{i n, p k}}}$
Capacitor	ESR, P_L,C,ESR	${I_{C, rms}}^{2} \times R_{ESR}$	$I_{C, avg} = 0; I_{C, rms} = \frac{I_{o}}{\sqrt{2}}$

[i] ESR, equivalent series resistance; f_s, Switching frequency; I_C_,avg, Average capacitor current; I_C_,rms, RMS capacitor current; I_D_,avg, Average diode current; I_D_,rms, RMS diode current; I_in,avg, Average input current; I_in,rms, RMS input current; I_L_,avg, Average inductor current; I_L_,rms, RMS inductor current; I_O, Output current; I_sw,avg, Average switch current; I_sw,rms, RMS switch current; PFC, power factor correction; P_v, Volumetric core loss density; r_d, diode dynamic resistance; RDS(on), MOSFET’s on-resistance; R_ESR, ESR of capacitor; t_f, Fall time; t_r, Rise time; V_c, Core volume; V_F, Diode forward voltage drop; V_in,pk, Peak input voltage; V_O, Output voltage.

Efficiency profile and PF performance of the proposed 900 W boost PFC prototype operating at a nominal input of 230Vrms. PF, power factor; PFC, power factor correction.

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DOI: https://doi.org/10.2478/pead-2026-0027 | Journal eISSN: 2543-4292 | Journal ISSN: 2451-0262

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Language: English

Page range: 418 - 444

Submitted on: Apr 28, 2026

Accepted on: Aug 10, 2026

Published on: Sep 12, 2026

Published by: Wroclaw University of Science and Technology

In partnership with: Paradigm Publishing Services

Keywords:

boost power factor correction,

capacitor charge transfer model,

desired time-domain transient performance,

frequency-differentiated modelling,

grid-aligned resonance tuning

Related subjects:

Computer sciences,

Artificial intelligence,

Engineering,

Electrical engineering,

Electronics

© 2026 Deepu E. Koshy, S. A. Kannan, T. K. Sindhu, M. P. Shreelakshmi, published by Wroclaw University of Science and Technology
This work is licensed under the Creative Commons Attribution 4.0 License.

Volume 11 (2026): Issue 1 (January 2026)

Design and Development of Boost PFC Converter for Medium-Power High-Voltage Power Supply

Figures & Tables

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Table 1.

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Table 4.

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Table 5.

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