A Reduced Switch Single-Source Multilevel Inverter with GA-Based Selective Harmonic Elimination

State	S₁	S₂	…	S_n	T₁	T₂	T₃	T₄	V_dc
1	0	0	…	0	0/1	1/0	0/1	1/0	0
2	1	0	…	0	1	0	1	0	+1
3	1	0	…	0	0	1	0	1	−1
4	0	1	…	0	1	0	1	0	+2
5	0	1	…	0	0	1	0	1	−2
6	0	0	…	0	1	0	1	0	+3
7	0	0	…	0	0	1	0	1	−3
⋮	⋮	⋮	…	⋮	⋮	⋮	⋮	⋮	⋮
⋮	⋮	⋮	…	⋮	⋮	⋮	⋮	⋮	⋮
N_level − 1	0	0	…	1	1	1	0	0	+n
N_level	0	0	…	1	0	0	1	1	−n

[i] RSSS, reduced switch single source; MLI, multilevel inverter.

Table 2.

Comparison of proposed RSSS MLI with recently developed MLI topologies.

MLI topologies	N_sw	N_DC	TSV
CHB MLI Najjar et al. (2016)	$2 (N_{level} - 1)$	$\frac{(N_{level} - 1)}{2}$	$2 (N_{level} - 1) V_{DC}$
MLI1 Oskuee et al. (2015)	$\frac{2 (N_{level} + 8)}{3}$	$\frac{(N_{level} - 1)}{2}$	$(3 N_{level} - 7) V_{DC}$
MLI2 Babaei et al. (2014a)	$(N_{level} + 3)$	$\frac{(N_{level} - 1)}{4}$	$2 (N_{level} - 1) V_{DC}$
MLI3 Lee et al. (2018)	$\frac{5 (N_{level} - 1)}{3}$	$\frac{(N_{level} - 1)}{2}$	$3 (N_{level} - 1) V_{DC}$
MLI4 Hsieh et al. (2016)	$\frac{2 (N_{level} - 1)}{3} + 4$	$\frac{N_{level}}{3}$	$(2 N_{level} + 8) V_{DC}$
MLI5 Jayabalan et al. (2017)	$(N_{level} + 1)$	$\frac{(N_{level} - 3)}{2}$	$35 \frac{(N_{level} - 1)}{4} V_{DC}$
MLI6 Babaei et al. (2014b)	$\frac{3 (N_{level} - 1)}{4}$	$\frac{(N_{level} - 1)}{4}$	$5 \frac{(N_{level} - 1)}{2} V_{DC}$
Proposed RSSS MLI	$\frac{(N_{level} - 1)}{2} + 4$	$\frac{(N_{level} - 1)}{2}$	$5 \frac{(N_{level} - 1)}{2} V_{DC}$

[i] CHB MLI, cascaded H-bridge multilevel inverter; MLI, multilevel inverters; RSSS, reduced switch single source; TSV, total standing voltage.

Number of switches against number of levels. CHB MLI, cascaded H-bridge multilevel inverter; MLI, multilevel inverters; RSSS, reduced switch single source.

Number of DC voltage source against number of levels. CHB MLI, cascaded H-bridge multilevel inverter; MLI, multilevel inverters; RSSS, reduced switch single source.

Value of TSV against number of levels. CHB MLI, cascaded H-bridge multilevel inverter; MLI, multilevel inverters; RSSS, reduced switch single source; TSV, total standing voltage.

Table 3.

Comparison of proposed RSSS MLI with recently developed MLI topologies between 2022 and 2025.

Ref.	Topology	No. of levels	Switch count	DC sources	Control/modulation	THD (%)	Efficiency (%)	Remarks
Goel et al. (2022)	Single DC-source 13-level MLI	13	10	1	Fundamental switching	∼8–10	∼95	Reduced device count but limited scalability
Kubendran et al. (2022)	Reduced-switch cascaded MLI	9–17	12	Multiple	Nearest level control	∼9–12	∼94	Suitable for EV applications but requires multiple sources
Jena et al. (2024)	Transformer-less switched-capacitor MLI	9	12	1	PWM-based control	16.48	∼94	Self-balancing capacitors but higher THD without filtering
Saravanan et al. (2024)	Reduced-device 31-level inverter	31	12	Multiple	SPWM	<8	∼95	Higher number of levels but increased circuit complexity
Mohanty et al. (2025)	Reduced-switch asymmetrical MLI	9–13	10–12	Multiple	PSO-optimised controller	∼7–9	∼95	Designed for DC microgrid applications
Awadelseed et al. (2026)	Switched-capacitor ANPC inverter	9	10–12	1	Optimised modulation	∼5–7	96.9	High efficiency but uses capacitor balancing circuitry
Proposed RSSS MLI	This work	9	8	1	GA-SHE	≈10.86	≈95	Reduced switch count with GA-based harmonic elimination

[i] EVs, electric vehicles; GA, genetic algorithms; GA-SHE, genetic algorithm selective harmonic elimination; MLI, multilevel inverters; PSO, particle swarm optimization; RSSS, reduced switch single source; THD, total harmonic distortion.

Table 4.

Comparison of performance of proposed RSSS MLI and recently developed MLI topologies.

Topology	Output levels	Power switches	DC sources	Diodes/capacitors	Voltage gain	TSV	Control technique	THD (%)	Remarks
CHB MLI Najjar et al. (2016)	9	16	4	0	High	High	PWM/SHE	8–12	Modular but high switch count
MLI1 Oskuee et al. (2015)	9	12	4	2	Medium	Medium	PWM	9–13	Moderate complexity
MLI2 Babaei et al. (2014)	9	10	3	2	Medium	Medium	PWM	10–14	Multiple DC sources
MLI3 Lee et al. (2018)	9	12	4	2	Medium	High	SPWM	9–12	Higher voltage stress
MLI4 Hsieh et al. (2016)	9	10	4	2	Medium	High	PWM	10–13	Increased circuit complexity
MLI5 Jayabalan et al. (2017)	9	10	3	2	Medium	High	SPWM	9–12	Higher TSV
MLI6 Babaei et al. (2014)	9	10	3	0	Medium	Medium	PWM	9–13	Reduced device count
Reduced Switched-Capacitor MLI Hosseinzadeh et al. (2022)	9	10–12	Multiple	Capacitors	High	Medium	PWM	<10	Requires capacitor voltage balancing
Reduced-switch cascaded MLI Kubendran et al. (2022)	9–17	12	Multiple	0	Medium	Medium	Nearest Level Control	9–12	Requires multiple sources
Generalised Multisource Inverter Hosseinzadeh et al. (2024)	9–13	12	Multiple	Capacitors	High	Medium	Model predictive control	<8	High control complexity
Multi-Source MLI Espinosa et al. (2025)	9	10–12	Multiple	Capacitors	High	Medium	PWM	<10	Flexible multi-source operation
Proposed RSSS MLI	9	8	Single source	None	High	Low	GA-SHE	10.86	Reduced switch count and simplified control

[i] CHB MLI, cascaded H-bridge multilevel inverter; GA-SHE, genetic algorithm selective harmonic elimination; MLI, multilevel inverter; SHE, selective harmonic elimination; RSSS, reduced switch single source; MLI, multilevel inverter; THD, total harmonic distortion; TSV, total standing voltage.

Flowchart of GA for harmonic elimination. GA, genetic algorithm; THD, total harmonic distortion.

Table 5.

IGBT parameters.

V_dc	50 V
I_rms	2.16 A
V_T₀	0.8 V
V_D₀	1.1 V
T	20 ms
t_on	700 ns
t_off	450 ns

(a) Output voltage of nine-level RSSS MLI using RL-load. (b) Output current of nine-level RSSS MLI using RL-load. MLIs, multilevel inverters; RL, resistive–inductive load; RSSS, reduced switch single source.

(a) Variations of switching angles with modulation index. (b) Variations of THD with modulation index. THD, total harmonic distortion.

(a) THD analysis of output voltage of nine-level RSSS MLI. (b) THD analysis of output current of nine level RSSS MLI. MLI, multilevel inverter; RSSS, reduced switch single source; THD, total harmonic distortion.

Table 6.

Variation of switching angles with modulation index.

Modulation index	θ₁	θ₂	θ₃	θ₄
1.000	8.4389	19.2314	36.1245	57.3176
0.950	9.1926	19.5797	36.4326	58.9095
0.925	9.9500	20.0029	37.2343	59.1851
0.900	10.4054	20.4507	38.0021	59.4559
0.850	11.4501	21.2809	38.9241	60.0872
0.825	12.0383	21.5013	39.5321	60.4146
0.800	13.4202	22.5694	39.8726	61.2269
0.750	14.3501	22.8389	40.2547	62.0705
0.725	14.8955	23.4178	40.9432	62.0796
0.700	15.2552	24.3045	41.3125	62.7213
0.650	16.1434	24.9320	41.7658	63.2394
0.625	16.6702	25.6596	42.4325	64.1026
0.600	17.0195	26.4618	42.8654	64.6620

Table 7.

Variations of THD with modulation index.

Modulation index	Output voltage THD (%)	Output current THD (%)
1	9.64	3.08
0.950	10.86	3.32
0.925	11.53	4.09
0.900	12.77	4.33
0.850	12.48	5.20
0.825	12.42	4.61
0.800	12.25	4.15
0.750	12.92	3.94
0.725	13.77	4.44
0.700	14.61	5.02
0.650	17.68	5.88
0.625	19.57	5.92
0.600	18.36	6.53

[i] THD, total harmonic distortion.

Hardware setup of proposed work. MLI, multilevel inverter; RSSS, reduced switch single source.

(a) Output voltage without load. (b) THD analysis without load. THD, total harmonic distortion.

(a) Output voltage with R-load. (b) Output power with R-load. R-load, resistive load.

(a) THD analysis of output voltage with R-load. (b) THD analysis of output current with R-load. R-load, resistive load; THD, total harmonic distortion.

(a) Output voltage with RL-load. (b) Output power with RL-load. RL-load, resistive–inductive load.

(a) THD analysis of output voltage with RL-load. (b) THD analysis of output current with RL-load. RL-load, resistive–inductive load; THD, total harmonic distortion.

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DOI: https://doi.org/10.2478/pead-2026-0010 | Journal eISSN: 2543-4292 | Journal ISSN: 2451-0262

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Language: English

Page range: 157 - 174

Submitted on: Jan 18, 2026

Accepted on: Mar 8, 2026

Published on: Apr 17, 2026

Published by: Wroclaw University of Science and Technology

In partnership with: Paradigm Publishing Services

Keywords:

genetic algorithm,

multilevel inverter,

reduce switch count,

selective harmonic elimination,

total harmonic distortion

Related subjects:

Computer sciences,

Artificial intelligence,

Engineering,

Electrical engineering,

Electronics

© 2026 Amrita Singh, Anita Kumari, Atul Raj Singh, Anant Kumar, Pranav Kumar, Ravi Ranjan Kumar, published by Wroclaw University of Science and Technology
This work is licensed under the Creative Commons Attribution 4.0 License.

Volume 11 (2026): Issue 1 (January 2026)

A Reduced Switch Single-Source Multilevel Inverter with GA-Based Selective Harmonic Elimination

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