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A Reduced Switch Single-Source Multilevel Inverter with GA-Based Selective Harmonic Elimination Cover

A Reduced Switch Single-Source Multilevel Inverter with GA-Based Selective Harmonic Elimination

Open Access
|Apr 2026

Figures & Tables

Figure 1.

Proposed topology. LGU, level generation unit; PGU, polarity generation unit.

Figure 2.

Number of switches against number of levels. CHB MLI, cascaded H-bridge multilevel inverter; MLI, multilevel inverters; RSSS, reduced switch single source.

Figure 3.

Number of DC voltage source against number of levels. CHB MLI, cascaded H-bridge multilevel inverter; MLI, multilevel inverters; RSSS, reduced switch single source.

Figure 4.

Value of TSV against number of levels. CHB MLI, cascaded H-bridge multilevel inverter; MLI, multilevel inverters; RSSS, reduced switch single source; TSV, total standing voltage.

Figure 5.

Flowchart of GA for harmonic elimination. GA, genetic algorithm; THD, total harmonic distortion.

Figure 6.

(a) Output voltage of nine-level RSSS MLI using RL-load. (b) Output current of nine-level RSSS MLI using RL-load. MLIs, multilevel inverters; RL, resistive–inductive load; RSSS, reduced switch single source.

Figure 7.

(a) Variations of switching angles with modulation index. (b) Variations of THD with modulation index. THD, total harmonic distortion.

Figure 8.

(a) THD analysis of output voltage of nine-level RSSS MLI. (b) THD analysis of output current of nine level RSSS MLI. MLI, multilevel inverter; RSSS, reduced switch single source; THD, total harmonic distortion.

Figure 9.

Hardware setup of proposed work. MLI, multilevel inverter; RSSS, reduced switch single source.

Figure 10.

(a) Output voltage without load. (b) THD analysis without load. THD, total harmonic distortion.

Figure 11.

(a) Output voltage with R-load. (b) Output power with R-load. R-load, resistive load.

Figure 12.

(a) THD analysis of output voltage with R-load. (b) THD analysis of output current with R-load. R-load, resistive load; THD, total harmonic distortion.

Figure 13.

(a) Output voltage with RL-load. (b) Output power with RL-load. RL-load, resistive–inductive load.

Figure 14.

(a) THD analysis of output voltage with RL-load. (b) THD analysis of output current with RL-load. RL-load, resistive–inductive load; THD, total harmonic distortion.

IGBT parameters_

Vdc50 V
Irms2.16 A
VT00.8 V
VD01.1 V
T20 ms
ton700 ns
toff450 ns

Comparison of proposed RSSS MLI with recently developed MLI topologies between 2022 and 2025_

Ref.TopologyNo. of levelsSwitch countDC sourcesControl/modulationTHD (%)Efficiency (%)Remarks
Goel et al. (2022)Single DC-source 13-level MLI13101Fundamental switching∼8–10∼95Reduced device count but limited scalability
Kubendran et al. (2022)Reduced-switch cascaded MLI9–1712MultipleNearest level control∼9–12∼94Suitable for EV applications but requires multiple sources
Jena et al. (2024)Transformer-less switched-capacitor MLI9121PWM-based control16.48∼94Self-balancing capacitors but higher THD without filtering
Saravanan et al. (2024)Reduced-device 31-level inverter3112MultipleSPWM<8∼95Higher number of levels but increased circuit complexity
Mohanty et al. (2025)Reduced-switch asymmetrical MLI9–1310–12MultiplePSO-optimised controller∼7–9∼95Designed for DC microgrid applications
Awadelseed et al. (2026)Switched-capacitor ANPC inverter910–121Optimised modulation∼5–796.9High efficiency but uses capacitor balancing circuitry
Proposed RSSS MLIThis work981GA-SHE≈10.86≈95Reduced switch count with GA-based harmonic elimination

Variation of switching angles with modulation index_

Modulation indexθ1θ2θ3θ4
1.0008.438919.231436.124557.3176
0.9509.192619.579736.432658.9095
0.9259.950020.002937.234359.1851
0.90010.405420.450738.002159.4559
0.85011.450121.280938.924160.0872
0.82512.038321.501339.532160.4146
0.80013.420222.569439.872661.2269
0.75014.350122.838940.254762.0705
0.72514.895523.417840.943262.0796
0.70015.255224.304541.312562.7213
0.65016.143424.932041.765863.2394
0.62516.670225.659642.432564.1026
0.60017.019526.461842.865464.6620

Variations of THD with modulation index_

Modulation indexOutput voltage THD (%)Output current THD (%)
19.643.08
0.95010.863.32
0.92511.534.09
0.90012.774.33
0.85012.485.20
0.82512.424.61
0.80012.254.15
0.75012.923.94
0.72513.774.44
0.70014.615.02
0.65017.685.88
0.62519.575.92
0.60018.366.53

Comparison of proposed RSSS MLI with recently developed MLI topologies_

MLI topologiesNswNDCTSV
CHB MLI Najjar et al. (2016) 2Nlevel1 2\left( {{N_{{\rm{level}}}} - 1} \right) Nlevel12 {{\left( {{N_{{\rm{level}}}} - 1} \right)} \over 2} 2Nlevel1VDC 2\left( {{N_{{\rm{level}}}} - 1} \right){V_{DC}}
MLI1 Oskuee et al. (2015) 2Nlevel+83 {{2\left( {{N_{{\rm{level}}}} + 8} \right)} \over 3} Nlevel12 {{\left( {{N_{{\rm{level}}}} - 1} \right)} \over 2} 3Nlevel7VDC \left( {3{N_{{\rm{level}}}} - 7} \right){V_{DC}}
MLI2 Babaei et al. (2014a) Nlevel+3 \left( {{N_{{\rm{level}}}} + 3} \right) Nlevel14 {{\left( {{N_{{\rm{level}}}} - 1} \right)} \over 4} 2Nlevel1VDC 2\left( {{N_{{\rm{level}}}} - 1} \right){V_{DC}}
MLI3 Lee et al. (2018) 5Nlevel13 {{5\left( {{N_{{\rm{level}}}} - 1} \right)} \over 3} Nlevel12 {{\left( {{N_{{\rm{level}}}} - 1} \right)} \over 2} 3Nlevel1VDC 3\left( {{N_{{\rm{level}}}} - 1} \right){V_{DC}}
MLI4 Hsieh et al. (2016) 2Nlevel13+4 {{2\left( {{N_{{\rm{level}}}} - 1} \right)} \over 3} + 4 Nlevel3 {{{N_{{\rm{level}}}}} \over 3} 2Nlevel+8VDC \left( {2{N_{{\rm{level}}}} + 8} \right){V_{DC}}
MLI5 Jayabalan et al. (2017) Nlevel+1 \left( {{N_{{\rm{level}}}} + 1} \right) Nlevel32 {{\left( {{N_{{\rm{level}}}} - 3} \right)} \over 2} 35Nlevel14VDC 35{{\left( {{N_{{\rm{level}}}} - 1} \right)} \over 4}{V_{DC}}
MLI6 Babaei et al. (2014b) 3Nlevel14 {{3\left( {{N_{{\rm{level}}}} - 1} \right)} \over 4} Nlevel14 {{\left( {{N_{{\rm{level}}}} - 1} \right)} \over 4} 5Nlevel12VDC 5{{\left( {{N_{{\rm{level}}}} - 1} \right)} \over 2}{V_{DC}}
Proposed RSSS MLI Nlevel12+4 {{\left( {{N_{{\rm{level}}}} - 1} \right)} \over 2} + 4 Nlevel12 {{\left( {{N_{{\rm{level}}}} - 1} \right)} \over 2} 5Nlevel12VDC 5{{\left( {{N_{{\rm{level}}}} - 1} \right)} \over 2}{V_{DC}}

Switching sequence of proposed RSSS MLI_

StateS1S2SnT1T2T3T4Vdc
10000/11/00/11/00
21001010+1
31000101−1
40101010+2
50100101−2
60001010+3
70000101−3
Nlevel − 10011100+n
Nlevel0010011−n

Comparison of performance of proposed RSSS MLI and recently developed MLI topologies_

TopologyOutput levelsPower switchesDC sourcesDiodes/capacitorsVoltage gainTSVControl techniqueTHD (%)Remarks
CHB MLI Najjar et al. (2016)91640HighHighPWM/SHE8–12Modular but high switch count
MLI1 Oskuee et al. (2015)91242MediumMediumPWM9–13Moderate complexity
MLI2 Babaei et al. (2014)91032MediumMediumPWM10–14Multiple DC sources
MLI3 Lee et al. (2018)91242MediumHighSPWM9–12Higher voltage stress
MLI4 Hsieh et al. (2016)91042MediumHighPWM10–13Increased circuit complexity
MLI5 Jayabalan et al. (2017)91032MediumHighSPWM9–12Higher TSV
MLI6 Babaei et al. (2014)91030MediumMediumPWM9–13Reduced device count
Reduced Switched-Capacitor MLI Hosseinzadeh et al. (2022)910–12MultipleCapacitorsHighMediumPWM<10Requires capacitor voltage balancing
Reduced-switch cascaded MLI Kubendran et al. (2022)9–1712Multiple0MediumMediumNearest Level Control9–12Requires multiple sources
Generalised Multisource Inverter Hosseinzadeh et al. (2024)9–1312MultipleCapacitorsHighMediumModel predictive control<8High control complexity
Multi-Source MLI Espinosa et al. (2025)910–12MultipleCapacitorsHighMediumPWM<10Flexible multi-source operation
Proposed RSSS MLI98Single sourceNoneHighLowGA-SHE10.86Reduced switch count and simplified control
DOI: https://doi.org/10.2478/pead-2026-0010 | Journal eISSN: 2543-4292 | Journal ISSN: 2451-0262
Language: English
Page range: 157 - 174
Submitted on: Jan 18, 2026
Accepted on: Mar 8, 2026
Published on: Apr 17, 2026
In partnership with: Paradigm Publishing Services
Publication frequency: 1 issue per year

© 2026 Amrita Singh, Anita Kumari, Atul Raj Singh, Anant Kumar, Pranav Kumar, Ravi Ranjan Kumar, published by Wroclaw University of Science and Technology
This work is licensed under the Creative Commons Attribution 4.0 License.