Figure 1.
Schematic diagram details of proposed CSMLI. CSMLI, switched capacitor multilevel inverter; RB-IGBT, reverse block IGBT.
Figure 2.
Mode diagram for all active voltage levels (red is conduction path, green is charging path and black is non-conducting). (a) Mode diagram during 1 pu. (b) Mode diagram during 2 pu. (c) Mode diagram during 3 pu (d) Mode diagram during 4 pu.
Figure 3.
Mode 0th state for (a) level-generating circuit (b) H-bridge.
Table 1.
Switching states and capacitor status (positive half).
| Switching states of the switches in level-generating circuit | H-bridge | Capacitor status | Output voltage | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| S1 | S2 | S3 | S4 | S5 | H1 | H2 | H3 | H4 | C1 | C2 | Levels |
| 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | D | C | 0 pu |
| 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | C | - | 1 pu |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | D | C | 2 pu |
| 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | C | D | 3 pu |
| 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | D | D | 4 pu |
Figure 4.
(a) An example of instant voltage status of both capacitors during normal operation. (b) Typical SPWM output during 1 pu-voltage level, where upper band is 1 pu and lower band is 0 pu. (c) Logic circuitry for generating gate pulse for all switches.
Table 2.
Modified-switching states and capacitor status (during 1 pu).
| Switching states of the switches in level-generating circuit | H-bridge | Capacitor status | Output voltage | |||||||
|---|---|---|---|---|---|---|---|---|---|---|
| S1 | S2 | S3 | S4 | S5 | H1 | H2 | H4 | C1 | C2 | Levels |
| 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | C | - | 1 pu |
| 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | D | C | 0 pu |
| 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | C | - | 1 pu |
| 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | D | C | 0 pu |
Figure 5.
Shaded portion shows the discharge of C1 due to load current from t4 to t4’ interval.
Table 3.
Comparison of device count.
| T | NL | Nv | Ns | Nd | Nc | Extension to higher levels |
|---|---|---|---|---|---|---|
| Sarwer et al. (2020) | 7 | 2 | 8 | 2 | 1 | No mention |
| Roy et al. (2021) | 7 | 1 | 9 | 2 | 3 | No mention |
| Iqbal et al. (2021b) | 9 | 1 | 10 | 1 | 2 | No mention |
| Panda et al. (2023) | 9 | 1 | 10 | 3 | 2 | Yes |
| Barzegarkhoo et al. (2021) | 9 | 1 | 14 | 0 | 4 | Yes |
| Sathik (2024) | 9 | 1 | 10 | 2 | 5 | No mention |
| [P] | 9 | 1 | 9 | 1 | 2 | Yes |
Table 4.
Comparison of performance.
| T | K | TSV | Fc | Ripple loss (W) | Conduction loss (W) | Efficiency (%) | Remarks |
|---|---|---|---|---|---|---|---|
| Sarwer et al. (2020) | 1.5 | 14 | 6.28 | 1.75 | 0.35 | 94.1 | Poor use of capacitor voltage, multiple DC |
| Roy et al. (2021) | 3 | 13 | 1.71 | 2.85 | 0.3 | 93.8 | High conduction and switching loss |
| Iqbal et al. (2021b) | 4 | 20 | 1.19 | 1.85 | 0.36 | 94.1 | Capacitor instability |
| Panda et al. (2023) | 4 | 18 | 1.19 | 1.91 | 0.42 | 93.1 | Insufficient charge to capacitor |
| Barzegarkhoo et al. (2021) | 4 | 24 | 1.5 | 3.96 | 0.41 | 91.2 | Complex circuit, poor use of capacitors |
| Sathik (2024) | 2 | 9 | 3.25 | 2.85 | 0.45 | 92.5 | Low boost, high voltage droop |
| [P] | 4 | 22 | 1.16 | 1.5 | 0.35 | 96.1 | High TSV |
Figure 6.
Steady-state output results (a) Output voltage and current waveform for a resistive load of 48 Ω (b) Voltage profile of capacitors C1 and C2 with load of 50 Ω (c) Steady-state output voltage and current waveform for a resistive load of 48 ∠ 45°Ω (d) Steady-state voltage profile of capacitors C1 and C2 with load of 48∠ 45°Ω (e) Filtered output voltage and current profile for resistive load of 48∠ 45° Ω (f) Filtered output voltage and current profile for inductive load of 48 ∠ 45°Ω.
Figure 7.
Transient results (a) MI change from 0.95 to 0.6 (b) MI and frequency change simultaneously (c) MI change with frequency change and load change. MI, modulation index change.
Figure 8.
Experimental results (a) Output voltage and current for 48 Ω load. (b) Output voltage and current for 48∠ 45° Ω load. (c) Voltage and current profile of capacitor C1 and C2 for supplying load current of 3 A (d) THD of voltage. (e) THD of current (power quality analyser), (f) Hardware setup. THD, total harmonic distortion.
Figure 9.
Voltage stress across different switches (a) stress across switches S1, S2, and S3 (b) stress across switches S1, S2, and S5 (c) gate pulse sequence of switches S1, S2, and S3 (d) gate pulse sequence of switches S4, S5 and H1.
Figure 10.
Output during transient state (a) MI change, load change, and frequency change all at one instant (b) load change only. MI, modulation index change.
Figure 11.
Output during transient state (a) Efficiency curves vs load (b) Loss proportion analysis for 500 W load.
Figure 12.
Cascade connection for higher voltage levels.
Figure 13.
(a) Extension to three phase circuit (red colour represents R phase and green colour represents Y phase). (b) Clubbing H-bridges terminal to form a neutral point (N is neutral).