An Improved and Efficient High-Boost Switched Capacitor Multilevel Inverter

Renewable sources nowadays are quite lucrative option for harnessing energy. However, these sources require suitable power electronic converters to produce high-quality power (Hosseinpour et al., 2024; Seifi et al., 2024). Distributed generation offers advantages like reduced power conversion losses, reduced transmission losses, and lesser reactive power issues. The conventional inverters (two-level type) require bulk filters to compensate harmonics. So, many conventional inverters have been replaced by multilevel inverters (MLI) (Anand et al., 2023a; Saif et al., 2025) because of its numerous advantages. MLIs are popular due to many reasons such as lesser total standing voltage (TSV) of switches, lower total harmonic distortion (THD), economic feasibility, and lesser electromagnetic interference (Anand et al., 2023a,b; Kar et al., 2024; Kar et al., 2023a,b). Three basic types of MLI topologies are diode-clamped (Anand et al., 2023a), flying capacitor type (Ben Smida and Ben Ammar, 2010), and cascaded H-bridge (Kouro et al., 2010; Rodriguez et al., 2009). Diode-clamped and flying capacitor-based MLIs required many components, especially diodes in case of diode-clamped and capacitors in case of flying capacitor model. Hence, employing these types of traditional MLI to furnish higher number of voltage levels becomes impractical. Moreover, the traditional diode clamp design gives voltage imbalance normally due to the use of dividing capacitors (Nabae et al., 1981).

Cascaded H-bridge, on other hand, requires a lot of independent voltage sources (Niu et al., 2020). Hence the task of building a robust MLI with reduced components, higher efficiency, lower-voltage stress across the circuit components is a big challenge. Much of the research work is in progress on ‘switched capacitor multilevel inverter’ (CSMLI). The compact design and requirement of very fewer voltage sources have made CSMLI quite popular. CSMLI topology can give an inherent boost which other types of MLI cannot give. This is a big advantage of CSMLI. Because of these advantages CSMLI topologies have becomes quite suitable for renewable energy source integration (Hassan et al., 2023), as renewable source gives low-voltage DC output. Use of single voltage source would require single charging circuit; hence for charging the circuit, the CSMLI presents a good option. Recently, several CSMLI have been proposed. Certain problems such as voltage imbalance, voltage ripple across capacitors, and deep discharge are not taken very seriously but need to be considered in the long run (Azimi et al., 2020; Panda et al., 2021). MLIs described in Hosseinzadeh et al. (2022) use Ampere’s second rule of charging to avoid inrush capacitor current, but in order to do so, the boost factor should be compromised to just one. Raman et al. (2019) use two DC sources, two capacitors, nine switches, and three power diodes to constitute a nine-level MLI. As can be seen, the component count is high, and, additionally, it uses two independent DC sources. Azimi et al. (2020) also use higher component count to realise a 13-level MLI. The voltage boost in Raman et al. (2019) and Sandeep and Yaragatti (2018) is just equivalent to one. Abdel-Rahim and Wang (2020) produce a five-level MLI with one capacitor and one DC-voltage source. Here too, component count is more with respect to the number of voltage levels it can produce and comparatively poor utilisation of capacitor voltage to produce voltage levels. Sarwer et al. (2020) use two DC sources and a capacitor to form a seven-level MLI with eight switches offering a boost factor of 2. Roy et al. (2021), on other hand, give three times the boost factor; however it needs numerous switches. Siddique et al. (2023) propose a nine-level MLI (neutral-clamped) with two times boost factor. The MLI in Kumari et al. (2021) is a nine-level MLI with a boost factor of two times. However, (Kumari et al., 2021; Roy et al., 2021; Sarwer et al., 2020; Siddique et al., 2023) use comparatively higher number of components with respect to the number of voltage levels it can generate. Iqbal et al. (2021a) offer quadruple boost but still the component count is high.

The proposed work gives a nine-level MLI topology with a single DC source as its basic topology. Suitable extended versions can give much higher levels. Following points highlight the merit of both the proposed CSMLI topology.

• It consists of optimal number of components.

• A unique switching strategy ensures optimum charging and balance of capacitor voltage in CSMLI topology by Allowing more charging points to ensure lesser capacitor voltage ripple in CSMLI topology.

• It offers high boost (four times) at output terminal of CSMLI topology.

• The topology offers superior efficiency.

• The basic model can be easily extended for higher levels and also for three-phase networks.

Section 2 describes the overall circuit topologies and their operation. It describes the design aspects, specifying the factors that determine the choice of components. Section 4 shows vivid comparison of the proposed model with other existing similar CSMLI models. Section 5 discusses simulation and experimental results. Section 6 depicts suitable ways of extending the circuit to produce higher number of voltage levels. Finally, the paper ends with the concluding section.

Choice of proper components and ensuring their ratings are crucial for proper functioning of the proposed topology.

3.1.

Diode and switch design (for both switched-diode and switched-capacitor models)

The forward voltage drops, and the dynamic resistance of the diode decides the capacitor voltage profile and is a crucial factor in deciding the optimal performance of the proposed topology. The charging path of both the capacitors will have the diodes in their path. Hence, it is desired to have a low forward-voltage drop and low dynamic on-state resistance. The TSV and average current of diodes D₁ and D₂ are as follows.

(1) VS3=VS1=VD1=Vin {V_{S3}} = {V_{S1}} = {V_{D1}} = {V_{in}} (2) VS4=VS2=VS5=2 Vin {V_{S4}} = {V_{S2}} = {V_{S5}} = 2\;{V_{in}} (3) ID1=2∫t1t2ILsinwt.dt+∫t3t4ILsinwt.dt {I_{D1}} = 2\left( {\mathop \smallint \nolimits_{t1}^{t2} \left( {{I_L}} \right)\sin\left( {wt} \right).dt + \mathop \smallint \nolimits_{t3}^{t4} \left( {{I_L}} \right)\sin \left( {wt} \right).dt} \right) (4) ID2=2∫t1t3ILsinwt.dt {I_{D2}} = 2\left( {\mathop \smallint \nolimits_{t1}^{t3} \left( {{I_L}} \right)\sin \left( {wt} \right).dt} \right)

Where V_D1, V_S1, V_S2, V_S3, and V_S4 are TSV of diode D₁ and switches S1, S2, S3, and S4. V_in is the input DC voltage. I_D1 and I_D2 are the average diode currents of D₁ and D₂. I_L is the peak value of load current. The time snaps like t_0, t₁, t₂, t₃, and t₄ define the time at which the voltage level goes to 0 pu, 1 pu, 2 pu, 3 pu, and 4 pu, respectively. Any suitable Schottky diode such as SR360 (60 V, 3 amps) has low drop and low resistance, so can be a potential choice. The diode TSV is comparatively less; hence, for most of the lower- and medium-voltage application, the peak inverse voltage range of Schottky diode will fit. Schottky diodes can handle 3–5 amps of current (rms) and up to 30 A of surge current for 8 ms (approx.) and 70 amps for 4 ms. The charging inrush current can be well adjusted within these limits. For higher load, more than one such diode can be connected in parallel. For switches also, similar scenario follows. The TSV of switches S1 and S3 is V_in whereas TSV of S3, S4, and S5 is 2 V_in. The topology design ensures minimum TSV to all level-generating switches. Hence, a low-voltage or medium-voltage switch with high current capability will give effective performance. Switches such as IRF series MOSFET offer low impedance and very low voltage drop. For both switches and diodes, on-state resistance and low voltage drop are important for the performance of the proposed topology.

3.2.

Capacitors selection (switched-capacitor model)

Capacitor selection is based on two points: the charging and the discharging instants. Discharging instant is dependent on load current and its conduction time until next recharge. The charging time depends on the path resistance and the total amount of charging time available. Capacitor C1 discharge is maximum during 4 pu-voltage level. At 3 pu, it gets recharged (refer to Table 1). So, the discharge amount will be (5) ΔQC1=∫t4t4′ILsinwt.dt \Delta {Q_{C1}} = \mathop \smallint \nolimits_{t4}^{t4'} {I_L}\sin \left( {wt} \right).dt (6) ΔQC1=C1ΔV1 \Delta {Q_{C1}} = \left( {C1} \right)\left( {\Delta {V_1}} \right)

During 4th level band of output voltage, the voltage swings between 3 pu and 4 pu. During 3 pu-voltage level, C1 gets tikling recharge, where the voltage level in C1 improves to an extent. This voltage gain needs to be accounted.

(7) Ar2=4∫t4t4′sinwt.dt {A_{r2}} = 4\mathop \smallint \nolimits_{t4}^{t4'} \sin \left( {wt} \right).\left( {dt} \right) (8) 1.Δt4=Ar2 1.\left( {\Delta {t_4}} \right) = {A_{r2}} (9) Δt3=t4′−t4−Δt4 \Delta {t_3} = \left( {t4' - t4} \right) - \Delta {t_4}

The term ‘IL’ represents the peak value of load current. The amount of charge lost is shown in black region in Figure 5, which is computed in Eq. (7). ‘Ar2’ represents that area. The scripts t4 and t4′ denote the starting and ending time of 4th voltage-level band. Δt₄ and Δt₃ are average estimated time for which 4 pu and 3 pu level prevails. The amount of time for which 4 pu level prevails can be approximated according to Eq. (8). From this, the effective amount of time for which 3 pu level prevails can be approximated according to Eq. (9). Next, considering a maximum allowable voltage ripple of C1 as ΔV1* \Delta V_1^* using the transient state equation, the following relation can be established, where R_d and R_s are switch and diode resistance. ΔV1* \Delta V_1^* is the maximum allowable voltage droop (for C1), which can be chosen as 5% or 10% of the final steady state voltage achievable. ΔV₁ is the voltage ripple of C1, produced while conducting load current during 4 pu voltage level, and it can be calculated according to Eq. (6). ΔV1* \Delta V_1^* is user-defined. ΔV₂ is the voltage ripple of C2. Point to be noted is that if C1 functions perfect at 4 pu-voltage level, then it will definitely function well during other voltage levels because 4 pu-voltage level gives the highest current and causes maximum discharge.

(10) 1−ΔV1*=1+1−ΔV1−1e−Δt3/Rd+RsC1 1 - \Delta V_1^* = 1 + \left\{ {\left( {1 - \Delta {V_1}} \right) - 1} \right\}{e^{ - \Delta {t_3}/\left( {{R_d} + {R_s}} \right)C1}}

Figure 5.

Shaded portion shows the discharge of C1 due to load current from t4 to t4’ interval.

Simplifying the equation (11) ΔV1*ΔV1=eΔt3Rd+RsC1 {{\Delta V_1^*} \over {\Delta {V_1}}} = {e^{{{\Delta {t_3}} \over {\left( {{R_d} + {R_s}} \right)C1}}}}

For estimating capacitor C2, similar steps can be followed. C2 goes on a continuous conduction mode during 3 pu and 4 pu with no intermittent charging in between. So, discharge amount for C2 can be calculated as (12) ΔQC2=∫t3t3′ILsinwt.dt. \Delta {Q_{C2}} = \mathop \smallint \nolimits_{t3}^{t3'} {I_L}\sin \left( {wt} \right).dt. (13) ΔQC2=C2ΔV2. \Delta {Q_{C2}} = \left( {C2} \right)\left( {\Delta {V_2}} \right).

Charging of C2 takes place during 2 pu-voltage level but complete charging cannot take place as during the same time, and a significant proportion of capacitor charge goes to the load as well. Hence, charge gained during 2 pu level is ignored. Full charging of C2 can take place during 1 pu-voltage level when the voltage level swings to 0 pu (refer Figure 4). Necessary equations to work out while charging C2 are as follows (14) Ar1=∫t0t1sinwt.dt. {A_{r1}} = \mathop \smallint \nolimits_{t0}^{t1} \sin\left( {wt} \right).\left( {dt} \right). (15) 1.Δt1=Ar1. 1.\left( {\Delta {t_1}} \right) = {A_{r1}}. (16) ΔT0=t1−t0−Δt1. \Delta {T_0} = \left( {t1 - t0} \right) - \Delta {t_1}.

Ar1 represents area of conduction during 1 pu-voltage level Eq. (7). ‘Δt₁ʼ and ‘Δt₁ʼ represent averaged estimated time for which 1 pu- and 0 pu-voltage levels prevail.

(17) 2−ΔV2*=2+2−ΔV2−2e−ΔT0/Rd+2RsC1 2 - \Delta V_2^* = 2 + \left\{ {\left( {2 - \Delta {V_2}} \right) - 2} \right\}{e^{ - \Delta {T_0}/\left( {{R_d} + 2{R_s}} \right)C1}}

Simplifying the equation (18) ΔV2*ΔV2=eΔT0Rd+2RsC1. {{\Delta V_2^*} \over {\Delta {V_2}}} = {e^{{{\Delta {T_0}} \over {\left( {{R_d} + 2{R_s}} \right)C1}}}}. where ΔV2* \Delta V_2^* is the maximum allowable voltage droop (for C2) which needs to be chosen according to the application or the user’s interest.

A rigorous comparison with recently published and similar work is carried out and presented in detail to prove the merit of the circuit. Table 3 displays comparison with respect to the number of components and the device count. Table 4 shows comparison based on the performance parameters. The notations used in Table 3 such as N_L and N_v denote number of levels and number of DC-voltage sources. The terms N_s, N_d, and N_c denote the total number of switches, diodes, and capacitors used. The term T means topologies. In Table 4, the term K means boosting factor. The terms TSV and Fc TSV of all switches are in per unit and cost function, respectively. The cost function can be defined as follows.

(19) Fc=2Ns+Nd+Nc+TSVαNvNL1K {F_c} = {{\left\{ {2{N_s} + {N_d} + {N_c} + \left( {TSV} \right)\alpha } \right\}{N_v}} \over {{N_L}}}\left( {{1 \over K}} \right)

The term α in cost function denotes weightage factor of TSV with respect to the total number of the components used. At present, α value will be taken as 1 for easy and fair comparison. Alpha value >1 or <1 can be taken and a modified cost function can be designed for comparison for specific purposes. Two times Ns is taken to indicate switch and their gate driver circuit. Apart from the tabular comparison, a detailed analysis of the compared topology is presented. Sarwer et al. (2020) describe a seven-level MLI. One major problem with this MLI (Sarwer et al., 2020) is poor utilisation of DC source and capacitor voltage (Sarwer et al., 2020) use two DC sources of 1 pu each and a capacitor charged up to 2 pu. This combination could produce four discreet levels of voltage, but it can at the maximum produce three levels of voltage. This indicates poor utilisation of voltage cells and poor boost factor as well. The 3 pu-voltage level is supplied by the capacitor and one DC source in series. The capacitor with 2 pu-voltage supplies two times more power than the DC source. This will cause rapid discharge of the capacitor. The MLI in Roy et al. (2021) uses a high number of component count, especially switches. From Figures 2c and 2d of Roy et al. (2021), it is observed that for 2 pu level, four switches and, for 3 pu level, a total of five switches are traced. Hence, at higher-voltage level, a greater number of switches are involved, and this will produce higher conduction loss. The MLI in Roy et al. (2021) also makes higher number of switching transition between consecutive voltage levels. This makes the switching technique complex and difficult to incorporate. Switching loss becomes pronounced for high-frequency modulation.

The next section describes the challenges and shortcoming of the comparative analysis in detail. MLI in Iqbal et al. (2021b) describes a nine-level inverter. High component count and complexity of the overall circuit assembly is a demerit. By analysing Figure 2 of Iqbal et al. (2021b), it can be observed that C2 is not getting properly charged. Except during 2 V_dc, level there is no other scope. During 2 V_dc level, the load also demands the power. The problem is clearly described in Section 2 under the subheading ‘Switching Strategy and Charging Problem with C2’. Another mistake in the MLI (Iqbal et al., 2021b) is in the topology itself. Figure 2 of Iqbal et al. (2021b) shows the mode diagram, where it indicates if switch S9 is on then the current from capacitor C2 can get short-circuited via switch S9 and antiparallel diode of switch S10. Hence, this is a fundamental issue in Iqbal et al. (2021b), and under such condition, the circuit would fail to operate. MLI in Panda et al. (2023) makes a good try towards designing a nine-level quadruple boost MLI with optimum number of components. Panda et al. (2023) utilises the zeroth voltage level to charge capacitor C2 up to 2 pu. However, in one half cycle, there is only one such instant for C2 to get charged. Moreover, the duration of zeroth voltage level is very short. Hence, charging of C2 cannot be effective. During 2 pu-voltage level, the charging of C2 takes place, but it faces the same limitation as encountered by Iqbal et al. (2021b). The topology proposed by Panda et al. (2023) is restricted to a low-frequency-modulation technique; hence, additional charging states for C2 are not possible as proposed in the topology. MLI in Panda et al. (2023) also features its expandability, producing just two additional distinct voltage levels for four switches, two diodes, and one capacitor. Hence, such an extension is economically challenging for Panda et al. (2023) MLI. MLI in Barzegarkhoo et al. (2021) requires high device count as evident from Table 1. Barzegarkhoo et al. (2021) propose a five-level BM. Although Barzegarkhoo et al. (2021) claim a common ground formation as a big factor of novelty, many other parameters are compromised in their MLI. Eqs (1)–(9) of Barzegarkhoo et al. (2021) formulate necessary information for higher voltage levels. Analysing the equation, it can be realised that the extension to produce higher level is quite challenging both for circuit point of view and economically. A high switch count results in high conduction and switching losses. MLI in Barzegarkhoo et al. (2021) uses one DC source and two capacitors for five-level but boost factor is just two instead of three. It shows poor capacitor utilisation. Sathik (2024) describes a nine-level MLI. One of the demerits of Sathik (2024) MLI is that it uses a total of five capacitors and a DC source, but still voltage gain is limited to two. A higher number of capacitors leads to increased capacitor losses and reduced volumetric efficiency. From mode diagrams in Figure 3 of Sathik (2024), it can be observed that the DC source is not involved in supplying the load during any voltage level. The capacitors are solely supplying the load. This will create relatively higher voltage droop especially during the highest voltage level. Sathik (2024) is a clamped-type circuit and they have a natural demerit of capacitor voltage instability after prolonged use. On a comparative scale, the proposed topology design utilises minimum number of components to yield maximum boost with effective charging of capacitors, avoiding voltage imbalance or insufficient charge for capacitors to realise nine-level CSMLI. Based on this loss optimisation (especially ripple loss), the proposed topology shows a superior efficiency of 96% (Table 4).

For simulation, the components with specification are as follows. Capacitors of value 2,200 uF (C1) and 3,300 uF (C2) are taken. Input DC voltage of value 36 V is considered. The power and switching frequency are set at 60 Hz and 3 kHz, respectively. The following describes the steady-state outputs for the switched-capacitor model. Figure 6 shows output results under steady-state condition. It is worth noting that in Figure 6a, voltage droop during the topmost level is comparatively less with a load of 48 Ω. This is because C2 and C1 receive more charge with the unique switching technique. Figure 6b shows the respective voltage profile of capacitors C1 and C2. It can be seen that both capacitors more or less maintain a consistent flat voltage profile. Figure 6c shows output voltage and current for an R–L load of impedance 48 ∠ 45°Ω. Figure 6d shows the voltage profile of both the capacitors C1 and C2 and, as expected, both the voltage profile base remains nearly flat. Also, it can be seen that with inductive load, the load current becomes nearly sinusoidal with THD less than 3%. Figures 6e and 6f show the filtered waveform in the presence of LC filter (5 mH and 15 uF) for the resistive and inductive loads, respectively. In all the cases of filtered waveforms, the voltage and current THD remain below 5% limit, thus proving its usefulness in any possible grid application. Apart from these set of results, the test is also carried out for other types of loads with varying values of impedances with same value of LC filter. It has been observed the steady-state values of the waveforms not only are consistent but also give the THD content well below 5%. For example, for a set of resistive loads such as 30 Ω, 60 Ω, 100 Ω, 120 Ω, 150 Ω, and 200 Ω in the presence of LC filter, both steady-state current and voltage values show consistent performance giving a net THD in the range 3%–4%. Similarly, a set of inductive loads is also tested at its best to prove the usefulness of the circuit. For example, for a set of diverse inductive loads with varying impedance and power factor, angle like 15 ∠ 20°Ω, 30 ∠ 45°Ω, 60 ∠ 30°Ω, 90 ∠ 45°Ω, 120 ∠ 45°Ω, and 150 ∠ 65°Ω. were put to test the performance. It was observed that the load current steady-state value is nearly sinusoidal due to inherent filtering effect of inductive load in addition to the external LC filter giving THD in the range of 1%–2%. The output voltage for inductive loads showed THD values that were consistent with the limit of less than the 5% mark. The next set of figures shows the circuit performance under transient condition. Figure 7a shows the output wave performance in case of modulation index change (MI) from 0.95 to 0.6, in the presence of a resistive load of 60 Ω with LC filter. The point D marked in red colour shows the point of disturbance. It can be seen that both voltage and current comply perfectly to the change. Figure 7b shows the scenario of disturbance like former with another added-frequency change effect at the point of disturbance. Figure 7c shows two disturbances at two different points, D₁ and D₂. D₁ corresponds to MI change and frequency change instant (as in Figure 7b) and D₂ corresponds to load change instant. During D₂ point, the load changes from R–L (30 ∠ 40°Ω.) to 32 Ω R load. It can be seen that all waveforms maintain their consistency and synchronism with the load current. Thus, the performance confirms the robustness of the proposed topology. Hence, with successful confirmation of simulation results, the hardware validation can begin. The next section shows the performance of the proposed. topology in terms of an inbuilt laboratory-based utility scale model. For designing a utility-based hardware model proper choice of component is very important. For switches S1, S2, S3, S4, and S5 IRF540 (100 V, 25 A) MOSFET will be a fitting choice. For H-bridge switches (H1–H4) IRF200 MOSFET is considered. For diode, SB5100 (100 V, 5 A) is used. The switch S4 is required to be unidirectional, hence a SB5100 is used in series with IRF540 to make it function like a typical RB-IGBT switch. The DC voltage in this case is set at 36 V which is typically the output of an average solar panel and standard Li-ion or lead-acid battery pack. The passive filter circuit, which in this case is LC filter, is taken as 8 mH and 15 uF, respectively. Figure 8 shows output waveforms of the laboratory-based prototype model. Figures 8a and 8b show filtered voltage and current wave for a resistive (48 Ω) and inductive (48 ∠ 45°Ω) loads, respectively. Figure 8c shows the voltage profile and their inrush current profile for both the capacitors for a 3 A load current. It can be seen the voltage and current waves are nearly sinusoidal, and the voltage profile of both capacitors is nearly flat. Capacitor C1 gives a voltage ripple of 2 V and C2 gives a voltage ripple of neatly 4 V for 3 A output load current. The inrush current of C1 as indicated in Figure 8(c) shows a peak value of 7 A while for C2, the inrush current peak value is 10 A approximately. Figures 8d and 8e show THD figure for load voltage and current. The THD of current is very less, around 0.8% (<1%), while the voltage THD is also very less, settling at around 1.8%. This proves the effectiveness of the proposed circuit in utilising the small edance and power factor angle like 15 ∠ 20°Ω, 30 ∠ 45°Ω, 60 ∠ .30°Ω, 90 ∠ 45°Ω, 120 ∠ 45°Ω, and 150 ∠ 65°Ω, the THD comes in the range of 0.6%–2% for load current and 2%–4% for load voltage. The next set of figures (Fig. 9) shows the voltage stress or TSV pattern of different switches. The TSV pattern is recorded over a period of two full cycles to reveal the intrinsic details of the voltage pattern. It can be seen that all switches lower limit is 0 V except switch S4, which is −36 as it has to block a reverse voltage as well. It can be observed that the pattern that H1 switch represents actually is common to H-bridge switches as well. Remaining switches such as S1, S2, S3, S4, and S5 have their TSV as indicated in Figures 9a and 9b. Figures 9c and 9d indicate the gate pulse pattern of the switches.

Figure 6.

Steady-state output results (a) Output voltage and current waveform for a resistive load of 48 Ω (b) Voltage profile of capacitors C1 and C2 with load of 50 Ω (c) Steady-state output voltage and current waveform for a resistive load of 48 ∠ 45°Ω (d) Steady-state voltage profile of capacitors C1 and C2 with load of 48∠ 45°Ω (e) Filtered output voltage and current profile for resistive load of 48∠ 45° Ω (f) Filtered output voltage and current profile for inductive load of 48 ∠ 45°Ω.

Figure 7.

Transient results (a) MI change from 0.95 to 0.6 (b) MI and frequency change simultaneously (c) MI change with frequency change and load change. MI, modulation index change.

Figure 8.

Experimental results (a) Output voltage and current for 48 Ω load. (b) Output voltage and current for 48∠ 45° Ω load. (c) Voltage and current profile of capacitor C1 and C2 for supplying load current of 3 A (d) THD of voltage. (e) THD of current (power quality analyser), (f) Hardware setup. THD, total harmonic distortion.

Figure 9.

Voltage stress across different switches (a) stress across switches S1, S2, and S3 (b) stress across switches S1, S2, and S5 (c) gate pulse sequence of switches S1, S2, and S3 (d) gate pulse sequence of switches S4, S5 and H1.

Figure 10 investigates the transient analysis of the circuit and shows some figures highlighting the behaviour of the circuit during transient state. As can be seen, Figure 10a indicates output performance of the proposed topology under disturbed condition. Point ‘D’ indicates point of disturbance. Initially, an R–L load of 17 ∠ 30°Ω. is applied with a 60-Hz supply frequency and 0.6 MI. Then at point D, a sudden change in frequency, load impedance, and MI are introduced. The frequency is changed to 120 Hz, MI changed to 0.95, and load is changed from R–L type to pure resistive load of 29 Ω. It can be observed that the pf factor changes in accordance with the value of load current. The voltage wave immediately regains its full capacity with change in MI to 0.95. Overall, the waveform changes appear to settle with new conditions within one full cycle. Figure 10b shows a condition of absolute load change case where initially an R–L load of 20 ∠ 30°Ω. is applied, and then at point of disturbance D, the load is changed from R–L to pure resistive load of 48 Ω. It is observed after the initiation of change that the load current immediately comes in phase with voltage wave and shows a value of 3 A peak load current. It is also observed that the both voltage and current respond to the change in conditions within one quarter of the full cycle. It is necessary also to investigate the performance of the proposed topology in terms of efficiency and loss analysis. For demonstration purpose, Figure 11a shows the efficiency curve of proposed topology with respect to output power. It can be seen that the efficiency curves show a gradual fall with increase in load power. At 100 W, it registers a efficiency of 96.4%, and at 300 W, it gives an efficiency of 95.6%. When load is at 500 W, the efficiency is around 94%; then at 700 W it is 92.6%, and at 900 W it shows an efficiency of 90.6%. Figure 11b shows the proportion of each of the three prominent loss types taken at an average load power of 500 W.

Figure 10.

Output during transient state (a) MI change, load change, and frequency change all at one instant (b) load change only. MI, modulation index change.

Figure 11.

Output during transient state (a) Efficiency curves vs load (b) Loss proportion analysis for 500 W load.

The work till here describes a novel nine-level quadruple boost topology with all the required results to prove its novelty and specialty. It provides optimum performance efficiency and cost function. A natural way to explore further any basic MLI topology is by analyzing various ways it can be extended (keeping the basic circuit unchanged) to achieve higher level count. The basic quadruple boost nine-level topology can be creatively extended in various ways at the expense of a few additional components which, in exchange, can give much higher magnitude of level count, giving the overall sinusoidal wave very much close to the ideal one. The following are some of the ways the basic topology of nine level can be extended to achieve higher voltage level count.

The proposed topology can be extended in a suitable way for higher levels. The best extension is shown in Figure 12, which consists of two modules and connected back-to-back. The proposed topology is connected with another similar topology with back-to-back connection. If the first module’s input DC value is 1 pu, then the second module’s value would be set at 9 pu.

Figure 12.

Cascade connection for higher voltage levels.

Such a configuration is very simple and does not require any additional components for accomplishing the connection. It would be surprising if it can produce a total of 41 distinct levels. So, a perfect 81-level MLI model at the end would be accomplished. Another point about such configuration would be its natural and inherent path for reactive power flow. The reason it can produce such high number of levels is that it can use both additive and subtractive sides. The first module can produce a maximum of four voltage levels. The 5th voltage level would be produced by the difference between the input DC voltage of the second module and the maximum voltage value of the first module; hence 9 − 4 = 5 becomes the 5th level. Next, 9 − 3, 9 − 2, and so on with 9 bypassing the entire 1st module to yield the 9th voltage level. The next step is when nine comes subsequently in addition to the voltage level produced by the first level. This additive phase gives 10th level to 13th level of voltage. The 14th voltage level is generated when the 2nd module produces 18 units, a difference of four units compared to the 1st module, thereby producing 18 − 4 = 14th level of voltage. Next, 18 − 3, 18 − 2, and so on with 18 units bypassing the entire 1st module to yield 18th voltage level. Likewise, such permutation and combination would produce a total of 41 distinct voltage levels.

6.1.

Possibility of extension to three phase

The proposed circuit extension to a three-phase system is possible as depicted in Figure 13(a). The R phase is in red colour, and the Y phase is in green colour. Considering the figure complexity, the entire circuit is not shown and just R-phase and Y-phase are shown. Similarly, the B-phase can be extended. Keeping the DC voltage source common, the level–generating circuit (LG) circuit and their respective H-bridge circuit can be connected as shown in Figure 13(a). The basic multilevel inverter proposed consists of an input DC followed by a level-generating circuit and then a H-bridge for polarity reversal. The proposed three-phase circuit works well with isolated loads in each phase. But any unified three-phase loading becomes little tricky and identification of a common neutral point is to be considered. Each phase has its own H-bridge as shown in Figure 13(b). A possible way of forming common neutral along with R, Y, B line terminal would be what shown in Figure 13(b). As the basic circuit and its extended variant (with single DC input source) contain only one DC input source and hence a balanced three-phase circuit can be constructed. Thus, the formation of a three-phase MLI is seamless without the use of any extra DC source. Use of only one DC source is also advantageous considering such a configuration will require only one charging circuit and maximum power point tracker (MPPT) control. The problem of array mismatching in case of multiple PV integrated DC source is eliminated. Thus, the single DC source in the middle serving as input source for all the three phase simultaneously is an advantage from many points of view.

Figure 13.

(a) Extension to three phase circuit (red colour represents R phase and green colour represents Y phase). (b) Clubbing H-bridges terminal to form a neutral point (N is neutral).

This article discussed a novel, reduced component nine-level switched-CSMLI topology. It uses only one DC source and two capacitors. A unique switching scheme is discussed to mitigate insufficient capacitor voltage problem which is associated with majority of high-boost CSMLI. This is naturally stable and gives balanced capacitor voltage profile also. A vivid comparative analysis with similar other topologies in quantitative and qualitative terms is presented. Among the existing works, the proposed topology achieves the minimum cost function. Furthermore, a unique suitable and effective extension is proposed to produce higher number of voltage levels. A possible description is also given towards extending it to a three-phase model as well. Both the basic model and the extended model have inherent reactive power flows. Both simulation and experimental results have shown steady-state and transient output response to prove the merit and effectiveness of the circuit.