Hybrid DSTATCOM Design Using Deep Belief Networks for Enhanced Power Quality Assessment

Pappu Suneetha; Kanna Subba Ramaiah; Nagalamadaka Visali

doi:10.2478/pead-2026-0008

Introduction

Recognised as an effective means to resolve these power quality (PQ) challenges, the development of new devices for the electricity distribution system (EDS) is becoming more popular around the world (Bighash et al., 2018; Ouchen et al., 2017; Roldan-Perez et al., 2019). The development of power electronic devices for static conversion has been a recent focus of research for all industrial and civil sectors during the past few decades. To cope the distributed static compensator (DSTATCOM) performance under various loading scenarios, IEEE-519-2017 and EN-50160 PQ guidelines are imposed for maintaining the strict limits on total harmonic distortions (THDs) of source current (Ouchen et al., 2018; Ye et al., 2018; Ouchen et al., 2016). As a result, the newly deployed device will bring many changes in the EDS. Extensive literature reviews have been conducted on the design of adaptive control algorithm for [DSTATCOM]. The simulation studies are reported for certain limitations for dependent parameters, medium flexibility, power loss and cost. In this way, adaptive least mean square (ALMS) (Mangaraj and Panda, 2018), Kernel Hebbian LMS (Mangaraj and Panda, 2019), deep recurrent learning (DRL) (Zhang et al., 2020), and Delta Bar Delta (Shukl and Singh, 2020), Sparse LMS (Mangaraj and Panda, 2021), ADALINE LMS (Peng et al., 2021), deep learning (DL) (Balouji et al., 2022; Mangaraj et al., 2022), SVC-coupled (Mangaraj and Jogeswara, 2023) studies on DSTATCOM have been put forwarded for the different features. The ALMS technique was employed for DSTATCOM to control the PQ behaviour which results better robustness, poor convergence, low control flexibility and less cost and no use of passive filter. Then, KHLMS was employed for DSTATCOM to control the PQ behaviour, which results better robustness, good convergence, high control flexibility and medium cost. Later to this, the DRL technique was employed for DSTATCOM to control the PQ behaviour, which results better robustness, good convergence, high control flexibility and medium cost. Similarly, the Delta-Bar-Delta NN technique was employed for DSTATCOM to control the PQ behaviour, which results better robustness, good convergence, high control flexibility and medium cost. Then, The SLMS technique was employed for DSTATCOM to control the PQ behaviour, which results better robustness, good convergence, high control flexibility and medium cost. Next to this, the ADALINE-LMS technique was employed for DSTATCOM to control the PQ behaviour, which results better robustness, poor convergence, low control flexibility and less cost. The adaptive control of the SVS-coupled hybrid DSTATCOM exhibits relatively poor convergence speed and limited control flexibility due to the slower reactive power modulation and discrete firing angle control characteristics of the SVC. Finally, the DL technique was employed for DSTATCOM to control the PQ behaviour, which results in better robustness, good convergence, medium control flexibility and less cost.

The proposed deep belief learning network (DBLN) algorithm in this work avoids making assumptions about the presence and nature of idea drift and increases accuracy when there is a lack of training data (Du et al., 2018; Liu and Feng, 2017; Zhang et al., 2018). The presented approach builds the tuned weights using a primary buffer of training data. The considerably tuned weights are presented to generate the acceptable level of accuracy switching signal required for the controlled switching devices T1 to T6.

To enhance system stability and enable active damping, careful consideration has been given to the design of the inductor and capacitor for the LC-linked DSTATCOM. To offer improved PQ solutions with dynamic responsiveness, this work suggests an LC-coupled DSTATCOM (Hu et al., 2019; Ouchen et al., 2020). This allows for the regulation of the inverter part’s voltage stress, which in turn leads to a significant reduction in switching noise and system loss. Furthermore, in comparison to DSTATCOM, the LC-DSTATCOM operates satisfactorily throughout a wide compensation range (Faiz et al., 2020; Liu et al., 2019). The suggested LC-DSTATCOM is an affordable solution that offers improved source current harmonic reduction, source side power factor (p.f) correction, load compensation, load voltage regulation, and maintenance of a steady voltage across the DC-link capacitor.

In the literature, several types of neural Network control algorithms are presented for DSTATCOM, as shown in Table 1.

Table 1.

Comparison of different algorithms for analysis of filtering characteristics

Control algorithm	Year of publication	Robustness	Convergence capability	Control flexibility	Power loss	Cost	LC coupling	Filtering process
ALMS	2018	✓	×	-	-	-	×	Active
KHLMS	2019	✓	✓	---	---	--	×	Active
DRL	2020	✓	✓	---	--	--	×	Active
Delta-Bar-Delta NN	2020	✓	✓	--	--	--	×	Active
SLMS	2021	✓	✓	---	--	--	×	Active
ADALINE-LMS	2021	✓	×	-	-	-	×	Active
DL	2022	✓	✓	--	-	--	×	Active
DBLN	2023	✓	✓	---	-	--	✓	Hybrid

Notation used: ✓= Yes, × = No, -=Low, --=Medium, ---=High

ALMS, adaptive least mean square; DBLN, deep belief learning network; DL, deep learning; DRL, deep recurrent learning principles are proposed for the purpose of active filtering. No author has attempted to employ such a technique for hybrid filtering. The above literature review has been motivated by the author to suggest a DBLN technique-based LC-supported DSTATCOM to provide the behaviour for better convergence characteristics, better control capability, low power loss, less cost and better shunt compensation.

This solution is regarded as a distinctive solution, which usually involves component upgrade or installation of new equipment. The following are the different objectives of the proposed algorithm:

The DBLN learning mechanism supports distributed and parallel algorithms, advanced analytics, cost effectiveness and scalability.

It ensures switching losses and low conduction across DBLN based LC supported DSTATCOM.

Along with voltage, load balancing, harmonic mitigation of the source current, voltage regulation, PF improvement, and balancing of the source current, it achieves the lowered rating of the voltage source converter (VSC) of the DSTATCOM.

The fundamental current loop stable margin variation caused by LC resonance peak shifts to fit the robustness requirement is investigated in detail.

It performs smooth operation among digital signal processors and analogue components simultaneously.

In this research article, simulation results are obtained using MATLAB/Simulink software. Moreover, the whole sections are organised as follows. Section 2 introduces Design and modelling of DBLN-controlled DSTATCOM and LC-coupled supported DSTATCOM for 3P3W EDS. Section 3 presents the mathematical formulation of DBLN learning mechanism. Section 4 shows the simulation waveforms to prove the effectiveness of the DSTATCOM. Section 5 authenticates the usefulness of the DSTATCOM by developing the hardware setups. In Section 6, the accomplishments of the paper’s aims are finally summarised.

Circuit Description of the System

The circuit connection of the proposed DSTATCOM and DSTATCOM with LC coupling is shown in the Figures 1 and 2, respectively. Here, T₁,T₂ ………T₆ are represented by different IGBTs used for all three phases. The source, load and filtering currents are represented by i_s,i_l & i_c respectively. The compensator impedance is denoted by Z_C. Figure 3 shows the typical schematic diagram of VSC served as an inverter for DSTATCOM.

Design of LC Coupling and DBLN Algorithm

3.1.

Design of LC coupling and its analysis

The suggested blue colour parameter for both cases, as shown in Figure 4, is taken into consideration while selecting the stability margin for the LC coupling. The proportional integral controller transfer function on the DC side is given given $g (s) = k_{pa} + \frac{K_{ia}}{s}$ g\left( s \right) = {k_{pa}} + {{{K_{ia}}} \over s} where, 0 ≤ k_pa ≤ 10, and 0 ≤ k_ia ≤ 1.

This proposed algorithm is Boltzmann Machine based technique, which contains three input layers, three output layers and three computational layers. The main idea of latent featured and vector encoded weights, and conditional probability density function (CPDF) is utilised to obtain the updated weight. The Bode plot of LC filter is shown in Figure 4.

The LC circuit resonates at the switching frequency $f_{sw} = \frac{1}{\sqrt{L_{f} C_{f}}}$ {f_{sw}} = {1 \over {\sqrt {{L_f}{C_f}} }} . The L_f = 10 mH is considered for the value of C_f = 10μF and 50 μF. From this Figure 4, it is observed that the value of C_f =10μF is attenuated effectively the switching frequency due to narrow and peak range of the frequency.

3.2.

DBLN learning mechanism

The block diagram of the proposed DBLN mechanism is shown in Figure 5, which represents the complete structure for compensation performance. This proposed algorithm is Boltzmann Machine-based technique, which contains three input layers, three output layers and three computational layers. The main idea of latent features and vector encoded weights, and CPDF is utilised to obtain the updated weight. The following novelties of the proposed Deep Belief Network algorithm are presented below:

Tracking of input neurons and online learning mechanisms are attained by using Deep Belief Network algorithm smoothly.

The various supplying and loading conditions, like balanced source, unbalanced source, balanced with distorted source, and unbalanced with distorted source, can be selected to meet the international standard grid codes on PQ issues.

It exhibits less static error and achieves fast convergence.

Robustness, tracking and adaptive abilities under variable loading periodicity.

It performs better coordination between the input and output neurons to adopt its own learning rule subjected to different parameter variations, irrespective of time.

Figure 6 shows the flowchart for finding the tuned weight for compensation performance using the DBLN technique without and with LC coupling.

Figure 7 shows the learning mechanism adopted for obtaining the tuned weight for compensation performance using DBLN technique for the extraction of reactive part for a- phase. The complete procedures for weight updating are achieved which is explained in the subsequent section:

Here, j is considered as the neurons in the hidden layer and ‘i’ is the hidden neurons. The DBLN mechanism is used to extract the w_qa, w_qb, w_qc which are expressed by the following equation: (1) $W_{pc}^{n} = σ \sum_{k} W_{qa}^{n} h_{k}^{i - 1} u_{qa} (n) (i_{la} (n) - w_{qa} (n - 1)) + b_{j}^{i} w_{qa} (n - 1)$ W_{pc}^n = \sigma \sum\limits_k {W_{qa}^nh_k^{i - 1}{u_{qa}}\left( n \right)\left( {{i_{la}}\left( n \right) - {w_{qa}}\left( {n - 1} \right)} \right) + b_j^i{w_{qa}}\left( {n - 1} \right)} (2) $W_{qb}^{n} = σ \sum_{k} W_{qb}^{n} h_{k}^{i - 1} u_{qb} (n) (i_{lb} (n) - w_{qb} (n - 1)) + b_{j}^{i} w_{qb} (n - 1)$ W_{qb}^n = \sigma \sum\limits_k {W_{qb}^nh_k^{i - 1}{u_{qb}}\left( n \right)\left( {{i_{lb}}\left( n \right) - {w_{qb}}\left( {n - 1} \right)} \right) + b_j^i{w_{qb}}\left( {n - 1} \right)} (3) $W_{qc}^{n} = σ \sum_{k} W_{qc}^{n} h_{k}^{i - 1} u_{qc} (n) (i_{lc} (n) - w_{qc} (n - 1)) + b_{j}^{i} w_{qc} (n - 1)$ W_{qc}^n = \sigma \sum\limits_k {W_{qc}^nh_k^{i - 1}{u_{qc}}\left( n \right)\left( {{i_{lc}}\left( n \right) - {w_{qc}}\left( {n - 1} \right)} \right) + b_j^i{w_{qc}}\left( {n - 1} \right)}

In similarly manner the DBLN algorithm is used to extract w_pa, w_pb, w_pc which are represented by the following equation: (4) $W_{pa}^{n} = σ \sum_{k} W_{pa}^{n} h_{k}^{i - 1} u_{pa} (n) (i_{la} (n) - w_{pa} (n - 1)) + b_{j}^{i} w_{pa} (n - 1)$ W_{pa}^n = \sigma \sum\limits_k {W_{pa}^nh_k^{i - 1}{u_{pa}}\left( n \right)\left( {{i_{la}}\left( n \right) - {w_{pa}}\left( {n - 1} \right)} \right) + b_j^i{w_{pa}}\left( {n - 1} \right)} (5) $W_{pb}^{n} = σ \sum_{k} W_{pb}^{n} h_{k}^{i - 1} u_{pb} (n) (i_{la} (n) - w_{pb} (n - 1)) + b_{j}^{i} w_{pb} (n - 1)$ W_{pb}^n = \sigma \sum\limits_k {W_{pb}^nh_k^{i - 1}{u_{pb}}\left( n \right)\left( {{i_{la}}\left( n \right) - {w_{pb}}\left( {n - 1} \right)} \right) + b_j^i{w_{pb}}\left( {n - 1} \right)} (6) $W_{pc}^{n} = σ \sum_{k} W_{pc}^{n} h_{k}^{i - 1} u_{pc} (n) (i_{lc} (n) - w_{pc} (n - 1)) + b_{j}^{i} w_{pc} (n - 1)$ W_{pc}^n = \sigma \sum\limits_k {W_{pc}^nh_k^{i - 1}{u_{pc}}\left( n \right)\left( {{i_{lc}}\left( n \right) - {w_{pc}}\left( {n - 1} \right)} \right) + b_j^i{w_{pc}}\left( {n - 1} \right)}

The average reactive value is given as (7) $w_{r} = \frac{w_{qa} + w_{qb} + w_{qc}}{3}$ {w_r} = {{{w_{qa}} + {w_{qb}} + {w_{qc}}} \over 3}

Similarly, average active value is calculated as (8) $w_{a} = \frac{w_{pa} + w_{pb} + w_{pc}}{3}$ {w_a} = {{{w_{pa}} + {w_{pb}} + {w_{pc}}} \over 3}

The in-phase unit voltage templates (u_pa,u_pb, u_pc) are calculated from phase voltages (v_sa, v_sb, v_sc) & load voltage (v_t) which are given by: (9) $u_{pa} = \frac{v_{sa}}{v_{t}}, u_{pb} = \frac{v_{sb}}{v_{t}}, u_{pc} = \frac{v_{sc}}{v_{t}},$ {u_{pa}} = {{{v_{sa}}} \over {{v_t}}},{u_{pb}} = {{{v_{sb}}} \over {{v_t}}},{u_{pc}} = {{{v_{sc}}} \over {{v_t}}},

Similarly, the quadrature unit voltage templates (u_qa, u_qb, u_qc) are expressed by: (10) $u_{qa} = \frac{u_{pb} + u_{pc}}{\sqrt{3}}, u_{qb} = \frac{3 u_{pa} + u_{pb} - u_{pc}}{2 \sqrt{3}}, u_{qc} = \frac{- 3 u_{pa} + u_{pb} - u_{pc}}{2 \sqrt{3}}$ {u_{qa}} = {{{u_{pb}} + {u_{pc}}} \over {\sqrt 3 }},{u_{qb}} = {{3{u_{pa}} + {u_{pb}} - {u_{pc}}} \over {2\sqrt 3 }},{u_{qc}} = {{ - 3{u_{pa}} + {u_{pb}} - {u_{pc}}} \over {2\sqrt 3 }} Where, v_t can be expressed as (11) $v_{t} = \sqrt{\frac{2 (v_{sa}^{2} + v_{sb}^{2} + v_{sc}^{2})}{3}}$ {v_t} = \sqrt {{{2\left( {v_{sa}^2 + v_{sb}^2 + v_{sc}^2} \right)} \over 3}}

In order to regulate the constant DC bus voltage, the PI controller process the v_de signal, which is expressed as (12) $w_{cp} = k_{pa} v_{de} + k_{ia} \int v_{de} dt$ {w_{cp}} = {k_{pa}}{v_{de}} + {k_{ia}}\int {{v_{de}}dt} Where, v_de = v_{dc (ref)} − v_dc ;

The total active weight of the reference source current can be given in the form (13) $w_{sp} = w_{a} + w_{cp}$ {w_{sp}} = {w_a} + {w_{cp}} In order to regulate the constant AC bus voltage, the PI controller process the v_te signal, which is expressed as (14) $w_{cq} = k_{pr} v_{te} + k_{ir} \int v_{te} dt$ {w_{cq}} = {k_{pr}}{v_{te}} + {k_{ir}}\int {{v_{te}}dt} Where, v_te = v_{t (ref)} − v_t ;

Similarly, the total reactive weight component can be given in the form (15) $w_{sq} = w_{r} - w_{cq}$ {w_{sq}} = {w_r} - {w_{cq}} The active current component of the reference source is expressed as. (16) $i_{aa} = w_{sp} u_{qa}, i_{ab} = w_{sq} u_{qb}, i_{ac} = w_{sp} u_{qc}$ {i_{aa}} = {w_{sp}}{u_{qa}},{i_{ab}} = {w_{sq}}{u_{qb}},{i_{ac}} = {w_{sp}}{u_{qc}} Similarly, the reactive current component of the reference source is obtained as (17) $i_{ra} = w_{sq} u_{qa}, i_{rb} = w_{sq} u_{qb}, i_{rc} = w_{sq} u_{qc}$ {i_{ra}} = {w_{sq}}{u_{qa}},{i_{rb}} = {w_{sq}}{u_{qb}},{i_{rc}} = {w_{sq}}{u_{qc}} The reference source currents is formulated by the following equation (18) $i_{_{sa}}^{*} = i_{aa} + i_{ra}, i_{_{sb}}^{*} = i_{ab} + i_{rb}, i_{sc}^{*} = i_{ac} + i_{rc}$ i_{_{sa}}^* = {i_{aa}} + {i_{ra}},i_{_{sb}}^* = {i_{ab}} + {i_{rb}},i_{sc}^* = {i_{ac}} + {i_{rc}}

Simulation Results Using MATLAB

The performance of the system in order to verify the operation and response, the different case studies have been carried out. In addition, both the balanced and unbalanced loading states are considered to show the effectiveness which are explained in the subsequent section below:

4.1.

DBLN-based DSTATCOM

To demonstrate the effectiveness of the proposed DBLN-based DSTATCOM under both balanced and unbalanced loading is shown in the Figure 8a. The robustness is assessed for the non-linear load changes abruptly. The value of the non-linear load is maintained balanced during the time T₁ = 0.55 s to T₂ = 0.6 s and T₃ = 0.7 s to T₄ = 075 s. The unbalanced loading is shown by disconnecting ‘a’ phase load during the time T₁ = 0.6 s to T₁ = 0.7 s. The different subplots, such as supply voltage (v_s), corresponding current (i_s), load current (i_la,i_lb, i_lc,), compensating current (i_ca, i_cb, i_cc,) and corresponding voltage (v_dc) are arranged in this Figure 8a. The Figures 8b and 8c show the THD of the load and source current, respectively. It is observed that the control strategy provides the source current THD 4.67%. The attenuated harmonics and distortion percentage are remarkably less recommended standard IEEE 519-2017 [30]. The DC bus voltage is shown in Figure 8a, which also settles the desired reference value 671.9 V quickly without beyond limit of overshoot. To verify the p.f improvement, the ‘a’ phase source side voltage and current and load side voltage and current are shown in the Figures 8d and 8e, respectively.

4.2.

DBLN-based LC-supported DSTATCOM

To demonstrate the effectiveness of the proposed DBLN-based LC-supported DSTATCOM under both balanced and unbalanced loading is shown in the Figure 9a. The robustness is assessed for the non-linear load changes abruptly. The value of the non-linear load is maintained balanced during the time T₁ = 0.55 s to T₂ = 0.6 s and T₃ = 0.7 s to T₄ = 075 s. The different subplots such as supply voltage(v_s), corresponding current (i_s), load current (i_la, i_lb, i_lc), compensating current (i_ca, i_cb, i_cc), and corresponding voltage (v_dc) are arranged in this Figure 9a. The Figures 9b and 9c show the THD of the load and source current respectively. It is observed that the control strategy provides the THD 2.07% in the source current. The attenuated harmonics and distortion percentage are remarkably less recommended standard IEEE 519-2017 [30]. The dc bus voltage is shown in Figure 9a which also settled the desired reference value 605.6 V very quickly without beyond limit of overshoot. To verify the p.f improvement, the ‘a’ phase source side voltage and current and load side voltage and current are shown in the Figures 9d and 9e, respectively. The control strategy provides actual p.f improvement 0.99 in the supply side.

The desired load voltage remains invariable, which signifies voltage balancing in between load and DSTATCOM. To summarise, all these simulation results are presented to justify the robustness and dynamic response of the DBLN based LC supported DSTATCOM. The THD analysis for without DSTATCOM, DBLN-based DSTATCOM and DBLN-based LC-supported DSTATCOM for the three case studies is presented in the Table 2.

Table 2.

Comparative performance evaluation of different types of DSTATCOM.

Performance parameter	ALMS based DSTATCOM	DBLN based DSTATCOM	DBLN based LC supported DSTATCOM
i_s (A), %THD	55.88, 4.56	55.46, 4.07	54.46, 2.07
v_s (V), %THD	321.4, 2.54	321.4, 2.23	321, 1.42
i_l (A), %THD	42.96, 18.96	51.13, 20.64	51.13, 20.64
Power factor	0.94	0.97	0.99
v_dc (V)	680	671.6	605.6

ALMS, adaptive least mean square; DBLN, deep belief learning network; DSTATCOM, distributed static compensator; THD, total harmonic distortion.

Experimental Results of DBLN-Based LC-Supported DSTATCOM

To validate, an experimental setup is developed by assembling LC coupled VSI, non-linear load, dc-source, sources of supply, a compensating impedance, d-SPACE 1104, PQ Analyzer, as shown in Figure 10. The proposed DBLN mechanism contrivances in full digital system by encoding DSP (model no-TMSF28235). In this setup, power module (IPM 6MBP20RH60, 600 V, 20 A) is coupled with LC supported DSTATCOM. The switching signals are generated by dSPACE 1104 with a supply voltage of 230 V RMS for semiconductor switches, used in a power module. The dSPACE 1104, which allows the implementation of DBLN algorithm directly from the MATLAB/Simulink files. A multi-channel digital storage oscilloscope (scientific DSO-5100) stores the output waveform of the proposed topology with knob position sampling time 20 μs, voltage scale (200 V/div) and current scale (25 A/div).

It can be clearly observed that the Figures 11 and 12, are evaluated to analyse the PQ performance for DBLN based DSTATCOM and DBLN-based LC-coupled DSTATCOM. The remaining part of the experimental analysis detailed is presented in the subsequent sections.

As per the results, the Figures 11a and 11b present the source, compensator and load current using DBLN based DSTATCOM under balanced and unbalanced loading condition respectively. Here, the source current THD harmonic rate of 4.07% and 4.37% for the both the balanced and unbalanced loading is maintained is low but still meets the IEEE-519-2017 guidelines. Along with this, the source current becomes sinusoidal and balanced hence leads to improve PF 0.97 The DC voltage regulation with high stability and accuracy are maintained at 671.6 V. The PCC voltage magnitude and THD are 325 V and 2.23% maintained, which shows the voltage balancing.

To demonstrate the robustness of the DBLN based LC supported DSTATCOM, the following noteworthy points are evaluated as follows: As per the results, the Figures 12a and 12b present the source, compensator and load current using DBLN based LC supported DSTATCOM under balanced and unbalanced loading condition respectively. Here, the source current THD harmonic rate of 2.07% and 2.45% for the both the balanced and unbalanced loading is maintained which is quite low but still meets the IEEE-519-2017 guidelines. Along with this, the source current becomes sinusoidal and balanced hence leads to improve PF 0.99. The DC voltage regulation with high stability and accuracy are maintained at 605.6 V. The PCC voltage magnitude and THD are 325 V and 1.42% maintained, which shows the voltage balancing.

Finally, these above the necessary output of shunt compensation using DBLN-based LC-supported DSTATCOM is justified. The detailed simulation parameters and hardware configuration is presented in the Table 3.

Table 3.

Simulation/experimental parameters for proposed configuration.

Symbol	Definition	Value
v_s	3-phase source voltage	230 V/phase
f_s	Frequency	50 Hz
R_s	Source resistance	0.5 Ω
L_s	Source inductance	2 mH
L_f	Passive filter inductance	0.5 mH
C_f	Passive filter capacitance	10 μF
K_pr	AC proportional controller	0.2
C_dc	Capacitor	2,000 μF
K_pa	DC proportional controller	0.01
K_ia	DC integral controller	0.05
v_dc _(ref)	DC link voltage	650 V
R_c	VSC resistance	0.25 Ω
L_c	VSC inductance	1.5 mH
K_ir	AC integral controller	1.1

VSC, voltage source converter.

Conclusion

This paper addresses the experimental study of DBLN-based LC-supported DSTATCOM to show the better PQ improvement. The performance is analysed by using both simulation and experimental results. In the proposed DBLN based DSTATCOM, several advantages like noise elimination, higher efficiency, and better convergence characteristics, low power loss and better controllability are observed. In addition, the proposed DSTATCOM ensures stable operation because the following unique performance which is summarised below:

The DBLN-based LC-supported DSTATCOM THD harmonic rate of 3.37% and 3.37% for the both the balanced and unbalanced loading is maintained to meet the IEEE-519-2017 guidelines

The pf improvement is found which is effectively improved by using the proposed DSTATCOM

Three-phase source voltage and current are successfully balanced.

It is also inferred that the DC voltage regulation is maintained as per the standard guidelines of EN-50160.

It operates properly to maintain the balanced voltage under both the loading conditions.

With the proposed system, it can be analysed for integration of renewable energy with the existing AC EDS in future.

Hybrid DSTATCOM Design Using Deep Belief Networks for Enhanced Power Quality Assessment

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