Buck converter is the prominent and first generation member among the family of DC–DC converters (Rashid, 2004; Wu et al., 2015). In this, the necessities of soft-switching associated with various topologies of DC–DC converters have been illustrated. The hard-switching of self-commutating switching devices in power electronic circuits has been a major concern for researchers due to their various shortcomings. Hence, it results in an increase in the size of the heat sink, rating of filters, electromagnetic interference, etc. It finally leads to poor efficiency and so on. So it is the soft-switching mechanism (i.e., zero-voltage switching [ZVS] and zero-current switching [ZCS]) which can overcome these aforesaid problems. The fundamentals and the analysis of different DC–DC converters are covered (Rashid, 2004). Initially, the soft-switching is initiated with the load resonant technique, and later this technique went through its various developmental stages. The latest technique is terminated with a quasi-resonant technique. The researchers have utilised most preferred quasi-resonant principle for boost converter using single resonant network (Barreto et al., 2005). A soft-switching DC/DC converter with high voltage gain is presented (Do, 2010). This topology comprises two switches, four diodes, four capacitors, one source inductor and two pairs of coupled inductors. The researchers (Li et al., 2012) proposed the zero voltage transition (ZVT) principle, in which a very small interval of zero-voltage is created in a switching cycle for soft-switching using a quasi-resonant technique. Researchers (Gu et al., 2014; Prabhala et al., 2016; Siwakoti et al., 2014) proposed a high voltage DC–DC converter and a method of cancellation technique of current ripple at the input.
Prabhala et al., 2016 have incorporated two input boost stages for high voltage gain, whereas the researchers (Gu et al., 2014) suggested a technique for cancellation of current ripple at the input of the boost converter using a tapped inductor. To enable soft-switching the devices (Li et al., 2014), the converter possesses more than one switch and additional passive parameters. In some cases, they retain coupled inductors to drain out the primary current to the secondary, which appears to be complex because of a significant increase in components. A novel soft-switching DC–DC converter is proposed (Rathore et al., 2016). Here it is proposed a bi-directional soft-switching current-fed LCL resonant DC/DC converter is proposed to interface with a micro-grid, whereas Dobakhshari et al., 2017 have proposed a novel quasi-resonant current-fed converter with minimum switching losses. The researchers (Hosseinzadeh et al., 2019; Mohseni et al., 2020) proposed a soft-switching bidirectional step-up/step-down DC–DC converter. There has been proposed by researchers (Maulik et al., 2020) for a LCL resonant network and coupled inductor to enable soft-switching, but this phenomenon makes it bulky and complex to analyse the topologies. In literature (Behera et al., 2020), it has been emphasised to utilise the soft-switching technique for regulated power supply. Mohammadi et al., 2021 have presented a review paper listing a family of soft-switching DC–DC converters with two degrees of freedom in which the main topology is oriented in two different ways without the addition of any extra components to achieve desired performances. Hasanpour et al., 2021 proposed a new concept of using three winding coupled inductors along with a few other passive components for soft-switching for a fixed power rating, but in case of different ratings, it needs to redesign those coupled inductors. A separate secondary turn-off snubber is utilised for high-frequency soft-switching DC–DC converters (Pastor et al., 2022), whereas the researchers (Cheng et al., 2021) have highlighted the state-of-the-art on soft-switching technologies of DC–DC converters in their review paper. The inclusion of soft-switching technologies has been implemented in renewable power sources (Danyali et.al., 2022). The researchers (Yen and Chao, 2022) have proposed a topology comprising two switches, a coupled inductor along with multiple passive components and diodes, whereas the soft-switching technique (Forouzesh, 2022) has been extended to a three-phase AC-DC converter for power factor correction. Lalitha et al., 2022 have extended the soft-switching technique using ZVS for vehicle and grid applications with enhanced efficiency. On the contrary, it has been stressed the single-switch resonant principle for soft-switching DC–DC converter (Abbasian et al., 2022).
The researchers (Li et al., 2022; Yen and Chao, 2022) have proposed a two-switch topology with coupled inductors and other passive components for a soft-switched DC–DC converter. Researchers (Guan et.al., 2022, Kalahasthi et al., (2022 and 2023)) have included the high-gain soft-switching technique in DC–DC converter for renewable applications. It has been proposed a fully soft-switched non-isolated high step-down DC–DC converter (Khallili et al., 2023) with reduced voltage stress by using a number of switches and considerable passive components (i.e., three switches along with their anti-parallel diodes, five capacitors and two inductors).
Zhou et al., 2023 proposed a two-switch topology along with a considerable number of active and passive parameters (i.e., four capacitors, six diodes, two inductors) for soft switching of the devices. Researchers (Yan et al., 2023) have implemented the soft-switching technique for a bidirectional converter so as to extend its application for battery charging/discharging systems without sacrificing in minimising the ripple. Kalahasthi et al., 2023 have proposed a two-switch topology with two pairs of coupled inductors and five capacitors, which appears to be a significant increase in passive components. Similarly, the proposed topology (Montazerolghaem et al., 2023) contains two switches, two diodes, four inductors, one coupled inductor and four capacitors for step-down DC–DC converter. Such excessive passive components may not be attractive for researchers and commercially viable. Researchers (Pakdel et al., 2019) utilises a two-switch topology, one coupled inductor, one filter inductor, three diodes and three capacitors. Both switches are turned on ZVS and turned off under ZCS. Though the topology (Jahangiri et al., 2022) comprises a single switch, on the contrary, it possesses two pairs of coupled inductors, six diodes and two capacitors. Significant increase in the number of diodes and use of a coupled inductor make this topology less attractive.
From the above reviews, it is summarised that most of the researchers have used two or more switches, but with a significant number of passive components to facilitate soft-switching. In this paper, a novel two-switch topology with minimum passive components is proposed for a soft-switching buck converter. In a conventional buck converter, the filter inductor carries unidirectional current. But the filter inductor of the proposed topology carries bidirectional current, and the control technique for this converter is very simple. The proposed topology is analysed and validated through experimentation.
The conventional buck converter is shown in Figure 1. It comprises a semiconductor switch along with a snubber mechanism in parallel and a free-wheeling diode across the load. The anti-parallel diode across the switch acts as a feedback element and also as a protection tool for the switch. A low-pass filter is provided between the switching device and the load in order to minimise the ripple content in the output voltage. The prominent shortcomings in the conventional buck converter are the limitation in switching frequency, requirement of comparatively higher rating of filter parameters and heat sink, etc.
Conventional buck converter.
The conventional topology can be replaced by the proposed novel buck converter, which can perform with soft-switching as shown in Figure 2. The proposed topology comprises a pair of switches (one in series and the other across a shunt/dc link) and each switch is provided with an anti-parallel diode and high frequency snubber capacitor. The mid-point between the switches is connected to high-frequency filter inductor, followed by a filter capacitor connected across the load. The filter inductor and capacitor are designed in such a way that the current in the filter inductor becomes bidirectional with the alternate operation of two switches.
Proposed two-switch buck converter.
The principle of operation of the proposed converter is explained through Figures 3 and 4. Figure 3 shows a typical waveform for the explanation of the operation of the proposed topology during a switching cycle under steady state operation. The operation during a switching cycle is divided into eight modes of operation (i.e., Mode I to Mode VIII). These modes are shown in Figure 4. The dead time (i.e., time lag between the two switches when both of them are an off condition) is maintained during the transition of SW1 to SW2 and vice versa to enable soft-switching.
Typical waveforms during one cycle under steady-state operation.
Modes of operation (Modes I to IV). Modes of operation (Modes V to VIII).
Assuming that the snubber capacitor (CS2) across the DC link is charged to the source voltage and both devices across it (i.e., SW2 and D2) are in the off-state. The switch SW1 is turned on, but it is in the off state as its anti-parallel diode D1 is conducting the reversal current of the filter inductor. So the voltage across the snubber capacitor (i.e., CS1) is at zero due to the conduction of diode D1.
Mode I (t0∼t1): Though the switch (SW1) is already turned on prior to this mode, as stated in the initial condition, it does not conduct current as the diode D1 is forward-biased due to reverse current in the filter inductor. This mode (i.e., Figure 4a) starts when the diode D1 becomes reverse biased (i.e., when the reverse current in the filter inductor drops to zero) and the switch SW1 starts to carry current linearly from zero through the filter inductor. Thus, it provides power/energy to the parallel combination of load and filter capacitor. Now the direction of current in the filter inductor is from the source to the load. In this mode, the capacitor across switch (SW2) is clamped to the source voltage. The first mode ceases when the gating signal from SW1 is withdrawn.
Mode II (t1∼t2): In the second mode of the operation (Figure 4b), as the gate signal of SW1 is withdrawn, the current in the filter inductor diverts its path from switch SW1 to its parallel capacitors, CS1 and CS2. This instant is the initiation of Mode II. This capacitor CS1 gradually charges to the source voltage, whereas CS2 discharges to zero, which is the end of this mode. When the capacitor CS2 attains the magnitude of the source voltage, the voltage across SW2 falls to zero. So the DC link is virtually isolated from the source. During this mode, the current in the filter inductor decays. During the process of charging capacitor CS1, the series switch SW1 gets enough time for its turn-off under ZVS, as the charging time of CS1 is more than the turn-off time of SW1.
Mode III (t2∼t3): In the 3rd mode (i.e., Figure 4c), as the voltage across SW2 falls to zero, the current in the filter inductor diverts its path to the shunt diode (D2) across the shunt switch (SW2). This mode continues till the shunt switch SW2 is turned on.
Mode IV (t3∼t4): In the 4th mode of operation (i.e., Figure 4d), as the shunt switch SW2 is already turned on, but it does not carry current due to the forward-biased of its anti-parallel diode D2. This mode continues till the current in D2 falls to zero. This situation is the end of this mode, and the turn-on of the switch SW2 is under ZVS (i.e., at zero voltage due to conduction of diode D2).
Mode V (t4∼t5): In the 5th mode (i.e., Figure 4e), the current in the filter inductor reverses as the current in the shunt switch SW2 gradually increases from zero, which is the initiation of this mode. From the previous mode IV and current mode, it is concluded that the switch is turned on under ZVS, followed by ZCS, when the current in it starts from zero. This will continue till the gating signal of switch SW2 is withdrawn, which is the end of this mode.
Mode VI (t5∼t6): In the 6th mode of operation (i.e., Figure 4f), the gating signal from SW2 is withdrawn and the reversal of current in the filter inductor shifts from SW2 to the capacitors CS2 and CS1. The capacitor CS2 charges to the source voltage, and CS1 discharges to zero. Both charging and discharging processes occur simultaneously. At the end of this mode, the phenomena of charging and discharging of capacitors stops, but still the filter inductor retains some quantity of reversed current. The switch (SW2) is turned off under ZVS due to its parallel capacitor CS2, which is already at zero voltage level.
Mode VII (t6∼t7): In the 7th mode (i.e., Figure 4g), as the voltage across CS1 falls to zero due to the previous action, the reverse current of the filter inductor takes its path from the snubber capacitors to diode D1. This is the initiation of the mode, and this mode ceases when SW1 is turned on.
Mode VIII (t7∼t8): In 8th mode (i.e., Figure 4h), the series switch SW1 is provided with a gate pulse, but the diode D1 is already on in earlier modes due to reversal current in the filter inductor. So the conduction of SW1 gets delayed even if it is turned on. This mode would continue till the reversal current in the filter inductor (i.e., via diode D1) decays to zero. So this leads to soft-switching on for the switch SW1 under ZVS (i.e., due to conduction of diode D1), followed by ZCS (i.e., current in SW1 initiates from zero). After this mode, the switching cycle repeats again with Mode I.
This concept is completely innovative, as the snubber capacitors do not discharge their energies across their switches under steady-state operation, and this fact can be confirmed later from the simulation. The filter parameters of the proposed topology are designed in such a way that the filter inductor carries bidirectional current. The switch SW1 carries the rising portion of positive half current in the filter inductor, whereas its shunt switch SW2 carries the falling portion of negative half current in the filter inductor. A dead time is allowed between two switches not only to avoid a short-circuit across the DC link, but also to facilitate the charging of the capacitor across a switch, followed by the discharging of the capacitor across the other switch and vice versa. Also, it leads to the conduction of anti-parallel diodes. More clearly, it can be stated that before the conduction of SW2, the snubber capacitor CS1 is allowed to charge, followed by the discharging of CS2. This happens due to positive/forward current in the filter inductor during dead time, and it leads to conduction of the anti-parallel diode D2. So during the conduction of D2, SW2 is activated. The conduction of D2 creates a situation of zero voltage across switch SW2, which prevents its conduction, even though this switch is turned on. This would continue till the current in diode D2 decays to zero. After this situation, the SW2 would start to conduct with zero current. As a consequence, the conduction of SW2 gets delayed with respect to its initiation of gating pulse, and it leads to turn-on of this switch under ZVS, followed by ZCS.
A similar procedure repeats for SW1. Before SW1 is turned on, it is allowed to charge CS2 and discharge CS1 by the negative/reverse current in the filter inductor, followed by conduction of anti-parallel diode D1. During the conduction of diode D1, the SW1 is gated on, but it is delayed due to the conduction of diode D1. So this leads to its turn on under ZVS (i.e., due to conduction of diode D1), followed by ZCS (i.e., due to initiation of SW1 from zero current). When the gate signals are withdrawn from the switches, their currents are diverted through respective parallel snubber capacitors, which leads to turn off for the switches under ZVS.
The design of filter parameters for the discontinuous current in the filter inductor of conventional topology (Rashid, 2004) is required in this case, as these parameters need to be extended to the proposed topology to enable the bidirectional current in the filter inductor. This bidirectional current is achieved with the help of the alternate operation of its two switches.
In order to achieve discontinuous current through the filter inductor of a buck converter for soft-switching on, a proper design method is required. The filter inductor at the source (LF) and the filter capacitor across the load (CF) are designed as follows:
The design of filter parameters for discontinuous operation in the case of a conventional one is as follows.
The voltage across the series inductor LF of the buck converter is, in general
The ripple current in LF is assumed to rise linearly from Imin to Imax in time ton. Eq. (1) is rewritten as
The current in the filter inductor falls linearly from Imax to Imin in time toff. ‘ΔI’ is the difference between the peak and minimum value of ripple current. Eq. (2) is written under the off-period as follows.
On substituting ton = kT and toff = (1 − k) T (i.e., where k: duty ratio and T: switching period) in Eq. (8), it yields the average output voltage
If it is assumed a lossless circuit, then input power = output power
Vs Is = Vo Io = kVs Io and the average input current Is = k Io
The switching period (T) can be expressed using (3) and (6) as
The inductor current iLF can be expressed as
If the ripple current upon load is assumed to be small, then iLF = iCF.The average capacitor current that flows into the filter capacitor for the duration of ton + toff = T / 2 is
The load capacitor voltage is expressed as
Using ‘ΔI’ of Eq. (11) in (15), it yields
Eqs (11) and (16) are required to design the value of LF and CF, provided the ripple current and voltage are given.
Condition for verge of continuous current in the filter inductor and voltage across the filter capacitor:
If IL is the average inductor current, the maximum ripple current is ΔI = 2IL and substituting it in Eq. (11)
The average output/load current (IL) is expressed as
On substituting Eq. (18) into (17)
This Eq. (19) gives the critical value of inductor LCF by replacing LF by LCF in Eq. (19) (i.e., verge of continuous conduction of inductor current)
Similarly, if the VCF is the average capacitor voltage, the capacitor ripple voltage will be maximum when
On substituting Eq. (16) into (21), we can get
Since Vo = kVs, so Eq. (22) is replaced as
Eq. (23) results in getting the critical value of the capacitive filter. By replacing CF by CCF
Eqs (20) and (24) result in determining the critical values of the filter inductor and capacitor that give the information on the verge of continuous conduction for current in the filter inductor (LF) and voltage of filter capacitor (CF). So it indicates that the values of LF and CF below their critical values LCF and CCF lead to discontinuity in inductor current in the case of a conventional one, but bidirectional continuous current in the filter inductor of the proposed topology. But as per the requirement of the topology, it is needed a continuous bidirectional current in the filter inductor and a negligible ripple in voltage across the filter capacitor at the maximum permissible value of duty ratio. So the practical value of the filter inductor and capacitor would satisfy the following conditions.
The LCF and CCF (i.e., for the load resistance RL = 15 ohm, source voltage Vs = 30 V, switching frequency fsw = 40 kHz at a maximum permissible duty ratio of 0.85) to be considered for simulation are computed from Eqs (20) and (24) as follows.
The critical value of the filter inductor (LCF) is 28 μH, and the critical value of the filter capacitor CCF is 0.58 μF. But the actual value of the filter inductor and filter capacitor is based upon Eq. (25) are considered as 10 μH and 100 μF, respectively.
To design the value of snubber capacitors (CS1 and CS2) across switches, the following three parameters are required.
Peak current through filter inductor/switch
Device turn-off time (tq)
Source voltage (Vs)
The charging time (tc) for the snubber capacitor to be connected across the switch must be greater than the device turn-off time so as to facilitate soft-switching of the device. So this charging time (tc) is assumed to be twice the device turn-off time (tq), which can be obtained from the data sheet of the device.
The equation of charging of the snubber capacitor (CS = CS1 = CS2) is given by
On substituting Eq. (28) in (27), the expression of the snubber capacitor is given by
The rating of the snubber capacitor is obtained from Eq. (29) and is considered to be common for both series and shunt snubber capacitors. The value of the snubber capacitor is considered as 0.15 μF for both CS1 and CS2.
The dead time (Tdead) is provided (i.e., between turn-on of SW2 and turn-off of SW1 and vice versa) not only to avoid the short-circuiting across the DC link, but also to facilitate the soft-switching. The minimum dead time is the summation of the charging or discharging of snubber capacitors. Both charging and discharging of snubber capacitors take place simultaneously. The actual dead time is more than the charging or discharging time of snubber capacitors. So the minimum dead time is decided in such a way that before conducting any switch, its anti-parallel diode must be conducting. The switch would start to conduct when the anti-parallel diode across it stops conducting. The dead time is computed with the following equation.
The switches are activated with gate pulses during forward-biasing of their corresponding anti-parallel diodes, but switches do not conduct as it creates zero voltage across switches due to conduction of anti-parallel diodes. So this leads to ZVS operation. When these anti-parallel diodes come out of forward-biased condition, the switches start to conduct which leads to ZCS operation. Above all, it can be referred that switches are turned on under ZVS, followed by ZCS.
When switches are turned off, their corresponding snubber capacitors bypass the currents of the switches. The charging period of these capacitors needs to be more than the turn-off time of the switching device. So the snubber capacitors assist the switches to turn off ZVS operation.
The designed parameters of the proposed topology (i.e., at possibly maximum duty ratio [say kmax – 0.85], load resistance RL = 15 Ω, switching frequency fsw = 40 kHz and source voltage Vs = 30 V) are computed. Filter inductance = 10 μH, filter capacitor = 100 μF, snubber capacitances (CS1, CS2) = 0.15 μF and dead time (Tdead): 2 sμ.
The simulated results under MATLAB/Simulink environment under steady-state conditions are depicted in Figures 5–15. Figure 5 shows that the relevant waveforms are associated with switch SW1 at a duty ratio of 30%. The current waveforms of switch (SW1), snubber capacitor (CS1), diode current (D1), filter inductor (LF) and voltage across SW1 (i.e., same as VCS1) corresponding to its gate pulse Vg (SW1) are shown. It is observed that the current lags behind the initiation of the gate pulse Vg (SW1) by a delay time Td (SW1), as evident from the waveform. This delay is due to the conduction of its anti-parallel diode (D1). At this moment, the voltage across switch SW1 is zero, leading to the switch turning on under both ZVS, followed by ZCS.
Waveforms of currents in SW1, CS1, D1 and LF and voltage across SW1 and CS1 with respect to corresponding gate pulses at a duty-ratio of 30% and switching frequency fsw = 40 kHz.
Similar waveforms of currents and voltage across switch SW2 corresponding to its gate pulse Vg (SW2) are shown in Figure 6 at a duty ratio of 30%. It also shows the time delay in conduction of SW2 with respect to its gating pulse due to the conduction of the anti-parallel diode D2. Interestingly, the turn-off processes of both switches are simple as the currents in these switches are diverted to their respective parallel snubber capacitors, facilitating their soft-switching.
Waveforms of currents in SW2, CS2, D2 and LF and voltage across SW2 and CS2 with respect to corresponding gate pulses at a duty ratio of 30% and switching frequency fsw = 40 kHz.
Figures 7 and 8 show the relevant waveforms of switches SW1 and SW2 at a duty ratio of 60%, along with the current in the filter inductor (LF) with respect to the gating pulses of both switches. This differentiates the comparison of their soft-switching during the conduction of both switches. The current in the filter inductor is found to be bidirectional, and various part of it during different time intervals reflects the current through different components of this topology.
Waveforms of currents in SW1, CS1 and D1 with respect to the corresponding gate pulses Vg (SW1) at a duty ratio of 60%.
Waveforms of currents in SW2, CS2 and D2 with respect to the corresponding gate pulses Vg (SW2) at a duty ratio of 60%.
Figure 9 depicts the waveforms of currents in both SW1 and SW2, along with the filter inductor LF with respect to its gating pulse of SW1 at a duty ratio of 60%. So it can be differentiated with the instant of applying of gating pulses with dead time. In current waveform of the filter inductor shows the time delay of conduction of both switches with respect to their initiation of gating pulses.
Waveforms of currents in SW1 and SW2, filter inductor LF corresponding to their gating pulses of both switches at a duty ratio of 60% and switching frequency fsw = 40 kHz.
Figure 10 shows the gate pulses, currents, voltage across both switches, currents in both snubbers and in parallel diodes, along with the current of the filter inductor at a duty ratio of 60% for both switches. So it can be distinguished between waveforms associated with SW1 and SW2.
Waveforms of gate pulses, currents, voltage across switches (SW1, SW2), diode currents (D1 and D2), snubber capacitor currents (ICS1, ICS2) and current in filter inductor LF corresponding to their gating pulses of both switches at a duty ratio of 60% and switching frequency of 40 kHz.
The waveforms of currents in the filter inductor, filter capacitor and load, along with load voltage, are shown in Figure 11. According to Kirchhoff’s law, the current of the filter inductor is the sum of currents in the filter capacitor and load. The output voltage is found to be around ripple-free.
Waveforms of currents in filter inductor, filter capacitor, load and load voltage at a duty ratio of 60%.
Figures 12 and 3 show waveforms associated with SW1 and SW2 at a duty ratio of 30% and the average output voltage is nearly 8.3 V for an input of 30 V, which indicates buck operation. Also, the conduction of diode D1 shows power recovery for a short interval in a switching cycle.
Waveforms of currents in ISW1. ID1, VSW1 and Vo at a duty ratio of 30%.
Waveforms of currents in ISW2. ID2, VSW2 and Vo at a duty ratio of 30%.
Figure 14 shows the currents in both switches with respect to their respective gating pulses at a duty ratio of 30%. It also shows the output voltage profile from transient to steady-state at the same duty ratio. Similar waveforms are shown in Figure 15 at a duty ratio of 40% with an output voltage of 11.5 V. The operation under both duty ratios of 30% and 40% ensures buck operation and indicates that their voltage profiles are 8.3 V and 11.5 V, which are close to their ideal values (9 V and 12 V).
Waveforms of Vg (SW1), Vg (SW2), ISW1 and ISW2 for a few cycles and output voltage Vo at a duty ratio of 30% and input Vs = 30 V.
Waveforms of Vg (SW1), Vg (SW2), ISW1 and ISW2 for a few cycles and output voltage Vo at a duty ratio of 40% and input Vs = 30 V.
The output voltage profile of the proposed converter is given in Table 1. It shows the comparison between the ideal buck converter and the proposed buck converter. So it is observed that the proposed converter gives the least difference from the ideal one (i.e., follows the equation [Vo = k Vs]). Hence, it shows close to the linear operation of an ideal buck converter with variation in duty ratios.
Output voltage profile of the proposed buck converter for an input voltage of 30 V.
| K (%) | Output voltage of buck converter (V) | Output voltage of proposed buck converter(V) |
|---|---|---|
| 20 | 6 | 5.58 |
| 30 | 9 | 8.3 |
| 40 | 12 | 11.5 |
| 50 | 15 | 14.62 |
| 60 | 18 | 17.5 |
| 70 | 21 | 20.74 |
| 80 | 24 | 23.6 |
| 85 | 25.5 | 25.2 |
A prototype model is developed in the laboratory and experimented with the same parameters as considered in the simulation. The experimental results are given in Figures 16–18. Figures 16 and 17 show the experimental results of switch SW1 and SW2, respectively. Both figures show the current and voltage waveforms with respect to their gate pulses. These waveforms indicate that the currents in the switches are delayed with respect to the initiation of gating pulses. Simultaneously, it shows the ZVS on for the switches, followed by ZCS.
Waveforms of ISW1 and VSW1 at a duty ratio of 60%.
Waveforms of ISW2 and VSW2 at a duty ratio of 60%.
Waveforms of current in the filter inductor and load voltage with respect gating pulse of both switches at a duty ratio of 60%.
Figure 18 shows the experimental waveform of current in the filter inductor and load voltage (i.e., filter capacitor voltage) at a duty ratio of 60% with respect to gating pulses of both switches. The interval of dead time and delay time of both switches is reflected in the current waveform of the filter inductor. The current in the filter inductor shows bidirectional. So all these three experimental waveforms are justified with results obtained from simulation. The comparison between conventional and proposed half-bridge converters is given in Table 2. Also, Table 3 presents a comparison between the proposed structure and other structures published in past.
Comparison between the conventional half-bridge and the proposed half-bridge structure.
| Sl. No. | Conventional half-bridge converter | Proposed half-bridge structure |
|---|---|---|
| 1 | Snubber circuit contains three components (resistance, diode and capacitance) | The snubber circuit contains only capacitance |
| 2 | Filter ratings (LF and CF) are as per their designed values | A modified filter is required. The rating of the filter inductor is quite less, and the rating of the filter capacitor is very large as compared to a conventional one |
| 3 | Unidirectional current in the filter inductor | Bidirectional current in the filter inductor during each switching cycle |
| 4 | Hard switching of devices | Soft-switching of devices |
Performance comparison of various topologies.
| Components | Yen and Chao | Khalili et al. | Montezerolghaem et al. | Proposed structure |
|---|---|---|---|---|
| Switches | 4 | 2 | 2 | 2 |
| Diodes | 2 | 3 | 4 | 2 |
| Inductors coupling inductors | 2 | 1 | 4 | 1 |
| 1:2 | No | 1:1 (2) | No | |
| Capacitors | 1 | 5 | 4 | 3 |
| ZVS/ZCS | ZVS | ZVS | ZVS | Turn on under ZVS and ZCS. Turn off under ZVS |
ZCS, zero-current switching; ZVS, zero-voltage switching.
The idea of employing the suggested two-switch topology to achieve soft-switching is completely original and very different from previously suggested topologies. This topology is functioning satisfactorily under soft-switching on/off between specific duty-ratio ranges (i.e., 0.15 < = k < = 0.85). The dead time was introduced between switches to prevent short circuits over DC links and enable soft-switching of devices (i.e., by charging, discharging snubber capacitors and conduction of anti-parallel diodes). Bidirectional continuous current was discovered to flow through the filter inductor. Without dissipating through their respective switches, it was discovered that the snubber capacitors CS1 and CS2 return their energies to the source (i.e., while discharging) and load, respectively. The series and shunt switches turned on under both ZVS, followed by ZCS (i.e., ZVS due to conduction of anti-parallel diodes across switches and ZCS due to the delay in conduction of the switch). On the contrary, the switches were found to be turned off under ZVS due to its parallel snubber capacitors across them. The experimental results agree with the results obtained from the simulation. The proposed topology can be more suited to low to medium-power applications and can be extended to renewable applications.