Novel ternary logic gate circuits using CNTFET technology for energy-efficient design

Ternary logic, which utilizes three distinct logical states instead of the traditional two, is often considered a more effective alternative to binary logic. This increased state capacity can lead to benefits such as reduced chip size, lower power consumption, and faster response time. The special qualities of carbon nanotube field transistors (CNTFETs), namely their ability to alter diameter and achieve the required threshold voltage, are the foundation of STI design. Because of this characteristic, CNTFETs can be used with multiple-Vth design techniques. This paper presents new designs of ternary logic gates using CNTFET technology. The Synopsys HSPICE with 32 nm CNTFET technology is used to model a ternary inverter and universal gates. The proposed standard ternary inverter achieves a 74.45% reduction in power delay product compared to the existing design. Further, the proposed ternary NAND and NOR gates demonstrate a 50.95% and 81.85% reduction in average power consumption, respectively. Finally, the simulation results demonstrate that the proposed gates exhibit a significant improvement in the power-delay product and can be effectively utilized in energy-efficient designs.