Electronically tunable multiplier-free floating memtranstor emulator employing VDTA and VDCC

This work presents a compact floating configuration of the memtranstor (MT), a recently introduced memory element defined by the direct relationship between magnetic flux (φ) and charge (q). Unlike prior designs, the proposed emulator eliminates the need for multipliers or other complex circuitry, resulting in a simplified and power-efficient architecture. The circuit employs a single voltage differential transconductance amplifier (VDTA) and one voltage differential current conveyor (VDCC) as active devices, together with three grounded capacitors and one grounded electronic resistor as passive components. The emulator successfully reproduces the fundamental φ-q relationship and exhibits origin-crossing pinched hysteresis loops under sinusoidal excitation – a defining characteristic of memtranstive systems. It operates reliably at a supply voltage of ±0.9V and supports electronic tunability through adjustment of the VDTA and VDCC transconductance parameters), ensuring adaptability across a wide range of operating conditions. Extensive validation was carried out through mathematical modeling and LTSpice simulations based on a 180-nm CMOS process. The evaluation includes demonstration of memory effects, Monte Carlo analysis, temperature sensitivity studies, and characterization of pinched hysteresis loops under variations in DC control voltage, excitation frequency, and transconductance values. A full-custom layout was implemented, occupying a silicon area of 2529.49 μm². Non-ideal effects, including parasitics at active device terminals, were also thoroughly analyzed to ensure functional robustness. Distinguished by its compact structure, low component count, and ease of integration, the proposed design provides a robust and efficient platform for MT-based applications. Its demonstrated performance highlights significant potential for neuromorphic computing, chaos-based systems, nonlinear dynamics, and other emerging analog memory-oriented domains.