References
- “More Moore,” Int. Technol. Roadmap Semicond., pp. 1–52, 2015.
- S. Senni, L. Torres, G. Sassatelli, A. Gamatie, and B. Mussard, “Exploring MRAM Technologies for Energy Efficient Systems-On-Chip,” IEEE J. Emerg. Sel. Top. Circuits Syst., vol. 6, no. 3, pp. 279–292, 2016.
- H. S. P. Wong and S. Salahuddin, “Memory leads the way to better computing,” Nat. Nanotechnol., vol. 10, no. 3, pp. 191–194, 2015.
- S. Mittal and J. S. Vetter, “A Survey of Software Techniques for Using Non-Volatile Memories for Storage and Main Memory Systems,” IEEE Trans. Parallel Distrib. Syst., vol. 27, no. 5, pp. 1537–1550, 2016.
- Z. Guo, K. Cao, K. Shi, and W. Zhao, “Ultra-low power consumption spintronics devices,” in 2019 IEEE 13th International Conference on ASIC (ASICON), 2019, pp. 1–4.
- T. C. Chang, K. C. Chang, T. M. Tsai, T. J. Chu, and S. M. Sze, “Resistance random access memory,” Mater. Today, vol. 19, no. 5, pp. 254–264, Jun. 2016.
- F. Oboril, R. Bishnoi, M. Ebrahimi, and M. B. Tahoori, “Evaluation of hybrid memory technologies using SOTMRAM for on-chip cache hierarchy,” IEEE Trans. Comput. Des. Integr. Circuits Syst., vol. 34, no. 3, pp. 367–380, 2015.
- M. P. Komalan, C. Tenllado, J. I. G. Perez, F. T. Fernandez, and F. Catthoor, “System level exploration of a STT-MRAM based level 1 data-cache,” in Proceedings -Design, Automation and Test in Europe, DATE, 2015, vol. 2015-April, pp. 1311–1316.
- Z. Zhang, W. Wang, P. Yu, and Y. Jiang, “Cache performance of NV-STT-MRAM with scale effect and comparison with SRAM,” Int. J. Electron., vol. 109, no. 3, pp. 391–409, 2022.
- R. Saha, Y. P. Pundir, and P. Kumar Pal, “Comparative analysis of STT and SOT based MRAMs for last level caches,” J. Magn. Magn. Mater., vol. 551, p. 169161, Jun. 2022.
- T. Marinelli, J. I. G. Pérez, C. Tenllado, M. Komalan, M. Gupta, and F. Catthoor, “Microarchitectural Exploration of STT-MRAM Last-level Cache Parameters for Energy-efficient Devices,” ACM Trans. Embed. Comput. Syst., vol. 21, no. 1, pp. 1–20, 2022.
- X. Dong, N. P. Jouppi, and Y. Xie, “A circuit-architecture co-optimization framework for evaluating emerging memory hierarchies,” ISPASS 2013 - IEEE Int. Symp. Perform. Anal. Syst. Softw., pp. 140–141, 2013.
- S. Mittal and J. S. Vetter, “AYUSH: A Technique for Extending Lifetime of SRAM-NVM Hybrid Caches,” IEEE Comput. Archit. Lett., vol. 14, no. 2, pp. 115–118, Jul. 2015.
- R. Andrawis, A. Jaiswal, and K. Roy, “Design and Comparative Analysis of Spintronic Memories Based on Current and Voltage Driven Switching,” IEEE Trans. Electron Devices, vol. 65, no. 7, pp. 2682–2693, Jul. 2018.
- W. Kang, Y. Ran, Y. Zhang, W. Lv, and W. Zhao, “Modeling and Exploration of the Voltage-Controlled Magnetic Anisotropy Effect for the Next-Generation Low-Power and High-Speed MRAM Applications,” IEEE Trans. Nanotechnol., vol. 16, no. 3, pp. 387–395, 2017.
- X. Dong, C. Xu, N. Jouppi, and Y. Xie, “NVSim: A circuit-level performance, energy, and area model for emerging non-volatile memory,” IEEE Trans. Comput. Des. Integr. Circuits Syst., vol. 31, no. 7, pp. 994–1007, 2012.
- W. Kang, Y. Ran, Y. Zhang, W. Lv, and W. Zhao, “Modeling and Exploration of the Voltage-Controlled Magnetic Anisotropy Effect for the Next-Generation Low-Power and High-Speed MRAM Applications,” IEEE Trans. Nanotechnol., vol. 16, no. 3, pp. 387–395, May 2017.
- S. Shreya and B. K. Kaushik, “Modeling of Voltage-Controlled Spin-Orbit Torque MRAM for Multilevel Switching Application,” IEEE Trans. Electron Devices, vol. 67, no. 1, pp. 90–98, Jan. 2020.
- N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi, “CACTI 6.0: A Tool to Model Large Caches,” Symp. A Q. J. Mod. Foreign Lit., vol. HPL-2009-8, no. HPL-2009-85, pp. 0–24, 2009.
- I. Singh, B. Raj, M. Khosla, and B. K. Kaushik, “Comparative Analysis of Spintronic Memories for Low Power on-chip Caches,” SPIN, vol. 10, no. 04, p. 2050027, Dec. 2020.
- N. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 4th ed. USA: Addison-Wesley Publishing Company, 2010.
- R. Bishnoi, M. Ebrahimi, F. Oboril, and M. B. Tahoori, “Architectural aspects in design and analysis of SOT-based memories,” Proc. Asia South Pacific Des. Autom. Conf. ASPDAC, pp. 700–707, 2014.
- T. Wang, J. Q. Xiao, and X. Fan, “Spin-Orbit Torques in Metallic Magnetic Multilayers: Challenges and New Opportunities,” Spin, vol. 7, no. 3. p. 1740013, 2017.
- R. Ramaswamy, J. M. Lee, K. Cai, and H. Yang, “Recent advances in spin-orbit torques: Moving towards device applications,” Appl. Phys. Rev., vol. 5, no. 3, p. 031107, Aug. 2018.
- H. D. Kallinatha, S. Rai, and B. Talawar, “A Detailed Study of SOT-MRAM as an Alternative to DRAM Primary Memory in Multi-Core Environment,” IEEE Access, vol. 12, pp. 7224–7243, 2024.
- X. Xu, H. Zhang, C. Jiang, J. Li, S. Lu, Y. Li, H. Du, X. Zhang, Z. Wang, K. Cao, et al., “Full reliability characterization of three-terminal SOT-MTJ devices and corresponding arrays,” IEEE Int. Reliab. Phys. Symp. Proc., vol. 2023-March, 2023.
- Y. Seo and K. W. Kwon, “Ultra High-Density SOT-MRAM Design for Last-Level On-Chip Cache Application,” Electronics, vol. 12, no. 20, Oct. 2023.
- K. Tian, B. Wu, K. Chen, and W. Liu, “High-Performance Co-Processing Architecture Using SOT-MRAM-Based In-memory Computing Scheme,” Int. Symp. Circuits Syst., 2025.
- P. Kumar, D. E. Shim, and A. Naeemi, “Comprehensive Device to System Co-Design for SOT-MRAM at the 7 nm Node,” IEEE J. Explor. Solid-State Comput. Devices Circuits, 2025.
- A. Sura and V. Nehra, “Performance Comparison of Single Level STT and SOT MRAM Cells for Cache Applications,” 2021 25th Int. Symp. VLSI Des. Test, VDAT 2021, pp. 1–4, Sep. 2021.
- G. Yu, “Two-terminal MRAM with a spin,” Nat. Electron., vol. 1, no. 9, pp. 496–497, Sep. 2018.
- D. Mondal, A. Singh, S. Bhatt, and R. Mishra, “Hybrid Spin-Orbit Torque/Spin-Transfer Torque-Based Multibit Cell for Area-Efficient Magnetic Random Access Memory,” IEEE Trans. Electron Devices, vol. 70, no. 12, pp. 6318–6323, Dec. 2023.
- S. Han, Q. Wang, and Y. Jiang, “MRAM-based Cache System Design and Policy Optimization for RISC-V Multi-core CPUs,” IEEE Trans. Magn., pp. 1–14, 2023.
- S. Han, Q. Wang, and Y. Jiang, “Hierarchical cache configuration based on hybrid SOT- and STT-MRAM,” AIP Adv., vol. 13, no. 2, Feb. 2023.
- S. Zou, X. Zhao, Y. Xue, J. Gao, Y. Cui, and J. Luo, “Extremely Low Switching Current STT-MRAM Device With Double Spin Transfer Torque,” IEEE Electron Device Lett., vol. 46, no. 4, pp. 584–587, 2025.
- L. Chang, Z. Wang, Y. Gao, W. Kang, Y. Zhang, and W. Zhao, “Evaluation of spin-Hall-assisted STT-MRAM for cache replacement,” Nanoscale Archit. (NANOARCH), 2016 IEEE/ACM Int. Symp., pp. 73–78, 2016.
- D. Ielmini and G. Pedretti, “Resistive Switching Random-Access Memory (RRAM): Applications and Requirements for Memory and Computing,” Chem. Rev., vol. 125, no. 12, pp. 5584–5625, Jun. 2025.
- S. Kang, W. Y. Cho, B. H. Cho, K. J. Lee, C. S. Lee, H. R. Oh, B. G. Choi, Q. Wang, H. J. Kim, M. H. Park, et al., “A 0.1-μm 1.8-V 256-Mb Phase-change Random Access Memory (PRAM) with 66-MHz synchronous burst-read operation,” IEEE J. Solid-State Circuits, vol. 42, no. 1, pp. 210–216, 2007.
- S. Raoux, Y.-C. Chen, G. W. Burr, D. Krebs, R. M. Shelby, S.-H. Chen, H.-L. Lung, C. H. Lam, C. T. Rettner, M. J. Breitwisch, and M. Salinga, “Phase-change random access memory: A scalable technology,” IBM J. Res. Dev., vol. 52, no. 4.5, pp. 465–479, 2010.
- Y. Li and K. N. Quader, “NAND Flash memory: Challenges and opportunities,” Computer (Long. Beach. Calif)., vol. 46, no. 8, pp. 23–29, 2013.
- D. S. Jeong, R. Thomas, R. S. Katiyar, J. F. Scott, H. Kohlstedt, A. Petraru, and C. S. Hwang, “Emerging memories: resistive switching mechanisms and current status,” Reports Prog. Phys., vol. 75, no. 7, p. 76502, 2012.