A Ku band low-voltage and low-power CMOS low-noise amplifier with bulk isolation techniques

Guo, Zifeng; Liu, Jian

doi:10.2478/jee-2024-0014

Abstract

In this paper, a broadband(12-18G) low-noise amplifier (LNA) using 65-nm CMOS technology for satellite communication is presented. This LNA was designed in a cascode common source with inductive degeneration topology. In addition, the bulk isolation technique is employed to make the proposed LNA have a higher gain. Furthermore, a two-stage cascaded configuration combined with inductive parallel peaking technology is utilized to make the LNA achieve a wide operating band. For validation, we design this LNA in a 65nm CMOS technology. The simulated results show that S21 of 17.7dB ± 0.5dB, the input/output return loss of -10dB to -33dB and -12dB to -23dB, respectively. It offers the minimum noise figure (NF) performance of 3.33dB, reverse isolation(S12) better than 60dB, and third-order input point (IIP3) of -22.8 dBm obtained over the band of interest. Excluding the output buffer stage, the LNA is consuming 5.1 mW at a supply voltage of 0.8V and its layout area occupies 0.205 mm².

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A Ku band low-voltage and low-power CMOS low-noise amplifier with bulk isolation techniques

Abstract

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