Integrable emulation of a floating incremental/decremental inverse memristor for memristor bandwidth extension

Kapil Bhardwaj; Ravuri Narayana; Dheeraj Kalra; Mayank Srivastava

doi:10.2478/jee-2024-0001

Abstract

The article explores the compact emulation of the inverse memristor through a circuit-based approach. It introduces a floating emulator architecture that incorporates a dual output OTA (Operation Transconductance Amplifier) and DVCC (Differential Voltage Current Conveyor), along with two grounded passive elements, to achieve the emulation of an inverse memristor. The utilization of grounded resistance allows for tunability over the realized behaviour. A key contribution of this research is the novel application of the inverse memristor to extend the operating frequency range of any memristor emulator circuit. Validation of the proposed emulator circuit, in both incremental and decremental modes, along with its application, is conducted using PSPICE-generated simulation results in the 0.18 µm TSMC CMOS technology. Additionally, an inverse memristor emulator configuration employing the IC LM13700 is presented, and its functionality is tested through a breadboard implementation.

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Integrable emulation of a floating incremental/decremental inverse memristor for memristor bandwidth extension

Abstract

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