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Instruction mapping techniques for processors with very long instruction word architectures Cover

Instruction mapping techniques for processors with very long instruction word architectures

By: Roman Mego and  Tomas Fryza  
Open Access
|Dec 2022

References

  1. [1] H. Sutter, “The free lunch is over a fundamental turn toward concurrency in software”, Dr. Dobbs Journal, vol. 30, pp. 16–22, 2005.
  2. [2] A. Wang, E. Killian, D. Maydan, and C. Rowen, “Hardware/software instruction set configurability for system-on-chip processors”, Proceedings of the 38th Annual Design Automation Conference, ser, New York, NY, USA: Association for Computing Machinery, 2001, p. 184188, https://doi.org/10.1145/378239.378460.10.1145/378239.378460
  3. [3] D. Liu, Embedded DSP Processor Design: Application Specific Instruction Set Processors, CA, USA: Morgan Kaufmann Publishers Inc., 2008.10.1016/B978-012374123-3.50011-7
  4. [4] H. Javaid and S. Parameswaran, Pipelined Multiprocessor System-on-Chip for Multimedia, Switzerland: Springer, 2012.
  5. [5] M. Frankiewicz and A. Kos, “Microprocessor frequency control method under thermal and energy savings constraints”, IEEE Transactions on Components, Packaging and Manufacturing Technology, no. 12, pp. 1755–1762, 2015.10.1109/TCPMT.2015.2496876
  6. [6] W. Wolf, “Multiprocessor system-on-chip technology”, IEEE Signal Processing Magazine, no. 6, pp. 50–54, 2009.10.1109/MSP.2009.934138
  7. [7] J. Fisher, P. Faraboschi, and C. Young, Embedded computing: a VLIW approach to architecture, compilers and tools, 2005.
  8. [8] S. Rajagopalan, S. Rajan, S. Malik, S. Rigo, G. Araujo, and K. Takayama, “A retargetable vliw compiler framework for DSPS with instruction-level parallelism”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, no. 11, pp. 1319–1328, 2001.10.1109/43.959861
  9. [9] Y. Zeng, A. Gupta, and S. Malik, “Automatic generation of architecture-level models from RTL designs for processors and accelerators”, 2022 Design, Automation & Test Europe Conference & Exhibition (DATE), pp. 460–465.10.23919/DATE54114.2022.9774527
  10. [10] C. Fang, Z. Zhang, X. You, and C. Zhang, “Automatic hardware design tool based on reusing transformation”, 2019 IEEE 13th International Conference on ASIC (ASICON), pp. 1–4.10.1109/ASICON47005.2019.8983487
  11. [11] Y. Xing, B.-Y. Huang, A. Gupta, and S. Malik, “A formal instruction-level gpu model for scalable verification”, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 18, 2014, pp. 198–204.10.1145/3240765.3240771
  12. [12] M. Steuwer, T. Remmelg, and C. Dubach, “Lift: A functional data-parallel ir for high-performance GPU code generation”, 2017 IEEE/ACM International Symposium on Code Generation and Optimization (CGO), pp. 74–85.10.1109/CGO.2017.7863730
  13. [13] K. Ohno, T. Kamiya, T. Maruyama, and M. Matsumoto, “Automatic optimization of thread mapping for a GPGPU programming framework, Second International Symposium on Computing and Networking, 2014.10.1109/CANDAR.2014.104
  14. [14] E. Schnetter, “Performance and optimization abstractions for large scale heterogeneous systems in the cactus/chemora framework”, 2013 Extreme Scaling Workshop (xsw 2013), 2013, 33–42.10.1109/XSW.2013.9
  15. [15] Q. Wang, X. Zhang, Y. Zhang, and Q. Yi, “Augem: Automatically generate high performance dense linear algebra kernels on x86 cpus”, SC 13: Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis, 2013, 1–12.10.1145/2503210.2503219
  16. [16] T. Instruments, “TMS320C67x DSP Library Programmers Reference Guide”, Reference Guide, [Online]. Available: https://www.ti.com/lit/ug/spru657c/spru657c.pdf.
  17. [17] A. Limited, “Common Microcontroller Software Inter- face Standard (CMSIS)”, ARM, https://developer.arm.com/tools-and-software/embedded/cmsis.
  18. [18] W. von Hagen, The Definitive Guide to GCC, 2006.10.1007/978-1-4302-0219-6
  19. [19] K. D. Cooper and L. Torczon, Engineering a Compiler, 2011.
  20. [20] T. A. Mogensen, Introduction to Compiler Design, Switzerland: Springer, 2017.10.1007/978-3-319-66966-3
  21. [21] R. Mego and T. Fryza, “A tool for VLIW processors code optimizing”, 13th International Conference on Computer Engineering and Systems (ICCES), pp. 601–604, 2018.10.1109/ICCES.2018.8639186
  22. [22] T. Instruments, “TMS320C66x DSP CorePac User Guide”, User Guide, 2013, https://www.ti.com/lit/ug/sprugw0c/sprugw0c.pdf.
  23. [23] J. W. Cooley and J. W. Tukey, “An algorithm for the machine calculation of complex Fourier series”, Mathematics of Computation, pp. 297–301, 1965.10.1090/S0025-5718-1965-0178586-1
  24. [24] T. Fryza and R. Mego, “Low level source code optimizing for single/multi/core digital signal processors”, 23rd International Conference Radioelektronika (RADIOELEKTRONIKA, 2013), 288291, 2013.10.1109/RadioElek.2013.6530933
  25. [25] E. Gansner, E. Koutsofios, S. North, and K.-P. Vo, “A technique for drawing directed graphs”, IEEE Transactions on Software Engineering, no. 3, pp. 214–230, 1993.10.1109/32.221135
DOI: https://doi.org/10.2478/jee-2022-0053 | Journal eISSN: 1339-309X | Journal ISSN: 1335-3632
Language: English
Page range: 387 - 395
Submitted on: Sep 14, 2022
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Published on: Dec 24, 2022
In partnership with: Paradigm Publishing Services
Publication frequency: 6 issues per year

© 2022 Roman Mego, Tomas Fryza, published by Slovak University of Technology in Bratislava
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.