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Instruction mapping techniques for processors with very long instruction word architectures Cover

Instruction mapping techniques for processors with very long instruction word architectures

Journal of Electrical Engineering
Volume 73 (2022): Issue 6 (December 2022)
By: Roman Mego and  Tomas Fryza  
Open Access
|Dec 2022
Authors

Authors

Roman Mego

mego@vut.cz

Member, IEEE, Department of Radio electronics, Brno University of Technology, Brno, Czechia

Tomas Fryza

Senior Member, IEEE, Department of Radio electronics, Brno University of Technology, Brno, Czechia
DOI: https://doi.org/10.2478/jee-2022-0053 | Journal eISSN: 1339-309X | Journal ISSN: 1335-3632
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Language: English
Page range: 387 - 395
Submitted on: Sep 14, 2022
Published on: Dec 24, 2022
Published by: Slovak University of Technology in Bratislava
In partnership with: Paradigm Publishing Services
Publication frequency: 6 issues per year
Keywords:
digital signal processors,
parallel architectures,
low-level code,
instruction mapping,
signal-flow graph
Related subjects:
Engineering,
Introductions and overviews,
Engineering, other

© 2022 Roman Mego, Tomas Fryza, published by Slovak University of Technology in Bratislava
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.

Volume 73 (2022): Issue 6 (December 2022)
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