Modular Design Of Fast Leading Zeros Counting Circuit

Milenković, Nebojša Z.; Stanković, Vladimir V.; Milić, Miljana Lj.

doi:10.2478/jee-2015-0054

Abstract

In modern computing technique, calculation of leading zeros in a data represented as strings of digits is used very often. Those techniques require high speed of the circuit, as well as its fast design. In this paper we propose a design of such a counter, which is applicable to data length of w = 4j bits, for 4 < j ≤ 8. With this solution it is also possible to process longer data, since the suggested technique offers a good modularity. This is very important, considering the current technology scaling trends. In this paper, a delay behavior of the proposed circuit has also been investigated using equations and VHDL simulation based worst-case delay estimation method. The results show a significant improvement of the circuit speed, compared to the known solutions.

References

[1] OKLOBDZIJA, V. G. : An Algorithmic and Novel Design of a Leading Zero Detector Circuit: Comparison with Logic Synthesis, IEEE Trans. VLSI Systems 2 No. 1 (March 1994), 124–128.10.1109/92.273153
Search in Google Scholar
[2] SUZUKI, H.—MORINAKA, H.—MAKINO, H—NAKASE, Y. MASHIKO, K — SUMI, T. : Leading-zero anticipatory logic for high-speed floating point addition, IEICE Journal of Solid-State Circuits 31 No. 8 (August 1996), 1157–1164.10.1109/4.508263
Search in Google Scholar
[3] SCHMOOKLER, M. S.—NOVKA, K. J. : ”Leading Zero Anticipation and Detection - A Comparison of Methods, Proc. 15th IEEE Symposium on Computer Arithmetic (2001), 7–12.
Search in Google Scholar
[4] ARAKAWA, F. Hayashi,—T.—NISHIBORI, M. : An Exact Leading Non-Zero Detector for a Floating-Point Unit, IEICE Trans. Electron. E88-C No. 4 (April 2005), 570–575.10.1093/ietele/e88-c.4.570
Search in Google Scholar
[5] OTT, M. : Optimized Method and Aparatus for Parallel Leading Zero/One Detection, US Patent #6697828B1 (February 2004).
Search in Google Scholar
[6] YIN, S.-H.—GOWAN, M. K. : High Speed Leading or Trailing Bit Value Detection, US Patent #7012965B2 (March 2006).
Search in Google Scholar
[7] DIMITRAKOPOULOSG.—GALANOPOULOS, K.—MAVROKEFALIDIS, C.—NIKOLOS, D. : Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed Floating Point Units, IEEE Trans. On VLSI Systems 16 No. 7 (July 2008), 837–850.10.1109/TVLSI.2008.2000458
Search in Google Scholar
[8] WESTE, N.—HARRIS, D. : CMOS VLSI Design: A Circuit and System Perspective, third ed., Boston, MA Addison Wesley, 2005.
Search in Google Scholar
[9] TCBN65LP TSMC 65nm Cole Library Data Book, version 1.4, September 2008.
Search in Google Scholar
[10] SOKOLOVIC, M.—LITOVSKI, V. : Using VHDL simulator to estimate logic path delays in combinational and embedded sequential circuits, Proc. IEEE region 8 Eurocon 2005 Conference, Belgrade (2005), 547–550.10.1109/EURCON.2005.1630296
Search in Google Scholar
[11] M. SOKOLOVIC, V. LITOVSKI—M. ZWOLINSKI : New Concepts of Worst-Case Delay and Yield Estimation in Asynchronous VLSI Circuits, Microelectronics Reliability, Volume 49, Issue 2, pp. 186-198, February 2009.10.1016/j.microrel.2008.11.007
Search in Google Scholar
[12] SOKOLOVIC, M.—LITOVSKI, V—ZWOLINSKI, M. : Efficient and Realistic Statistical Worst Case Delay Computation Using VHDL, Electrical Engineering (Archive fur Elektrotechnik), 91 No. 4-5, 197–210, online: November 2009.10.1007/s00202-009-0133-y
Search in Google Scholar

Modular Design Of Fast Leading Zeros Counting Circuit

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