Table 1:
Comparative summary
| Platform | Architecture | Key strength | On-chip learning | Scale examples | Typical target |
|---|---|---|---|---|---|
| TrueNorth | Digital, event-driven | Extremely low-power inference; 1 M neurons/256 M synapses per chip | Limited (original designs) | 1 M neurons/chip (tiled) | Power-constrained inference |
| Loihi/Loihi 2 (Hala Point) | Digital, programmable spiking cores | Flexible neuron models, on-chip learning, research SDK | Yes (designed for it) | Hala Point: ∼1.15B neurons aggregated (Intel claims) | Adaptive learning, research |
| SpiNNaker | Many ARM cores, message multicast | Very large-scale, software-programmable SNN simulations | Via software simulation | Machines with >1 M cores; large SNN emulation | Neuroscience simulation |
| BrainScaleS-2 | Mixed-signal, accelerated analog dynamics | Time-accelerated emulation; study of dynamics/plasticity | Supported (hybrid) | Chip arrays/wafer modules for accelerated experiments | Experimental neuroscience, learning rule research |
| BrainChip Akida | Event-domain IP for edge | Commercial, productized low-power edge inference | Limited/targeted | IP blocks/small chips for edge devices | Edge AI products |
| DYNAP-SE2 (Dynap family) | Asynchronous multicore spiking | Compact, scalable research chips for low-power SNNs | Research features | Per-chip neurons ∼1k; multicore scaling | Low-power SNN experiments, embedded sensors |
Table 2:
Representative quantitative benchmarks with defined metrics
| Platform | Metric | Reported value | Defined as | Source |
|---|---|---|---|---|
| IBM TrueNorth | Power (static) | 65 mW/chip | Total chip power, real-time op. (1 kHz) | [18]; [4] |
| IBM TrueNorth | Energy/synaptic event | ∼26 pJ | Energy per synaptic operation, avg. over workload | [18] |
| IBM TrueNorth | Throughput efficiency | ∼46 GSOPS/W | Giga synaptic ops/sec, normalized to power | [18] |
| IBM TrueNorth | Scale | 1 M neurons/256 M synapses/chip | Neuron and synapse count, single 28 nm die | [4] |
| Intel Loihi | Energy/inference | ∼110.4 mJ (KWS benchmark) | Total energy/classification, dynamic + static | [29] |
| Intel Loihi | Inference latency | ∼4.8 ms | Input spike to output classification, wall-clock | [29] |
| Intel Loihi | Relative efficiency | ∼15× lower energy/inference versus Cortex-M7 | Ratio of energy/inference, same task | [29] |
| Loihi 2/Hala Point | Scale | 1.15B neurons; 128B synapses; 140,544 cores | Aggregate counts, 1,152 Loihi 2 chips | [30] |
| Loihi 2/Hala Point | System power | 2,600 W max (full system) | Total wall power, six-rack system, full load | [30] |
| Loihi 2/Hala Point | Throughput efficiency | Up to 15 TOPS/W (INT8, sparse DNN) | Tera 8-bit ops/sec per watt, 10:1 sparsity | [30] |
| SpiNNaker | Scale | >1 M ARM cores (SpiNNaker 1 M) | General-purpose ARM cores for SNN simulation | [3] |
Figure 1:
Neuromorphic platform decision flowchart. PCM, phase-change memory; SNN, spiking neural networks.
Figure 2:
Neuromorphic hardware platforms.
Figure 3:
Categories of neuromorphic learning. SNNs, spiking neural networks; STDP, spike-timing-dependent plasticity.
Table 3:
Learning mechanisms mapped to hardware requirements and on-chip support
| Learning rule | Required hardware infrastructure | Hardware platform constraint or support | Is the learning circuit on-chip? | Citation |
|---|---|---|---|---|
| STDP (pair/triplet/rate-based) | Neuron with weight-update circuit receiving pre- and post-spike timing signals without the need for a global error signal | Loihi/Loihi 2 (learning rules programmable), DYNAP-SE2 (analog STDP circuitry), memristive crossbars (conduction update = STDP function) | Yes | Sec. 5; [15] |
| Surrogate-gradient SNN training | Differentiable approximation of spike nonlinearity; requires BPTT or eligibilities | Training: Off-chip (GPU: SLAYER, snnTorch). In-the-loop training: BrainScaleS-2 (analog substrate involved in training loop) | Only BrainScaleS-2 among those surveyed supports partial in-the-loop capability | [33, 34] |
| Conversion of ANN to SNN | Requires only inference spiking hardware; learning circuit not necessary because weights are trained off-chip | TrueNorth (Eedn toolkit), Loihi/Loihi 2 using Lava-DL, SpiNNaker using SNN Toolbox | Not applicable (by design) | [12, 32] |
| Reward-modulated STDP/three-factor rules | Requires an additional modulatory signal channel along with pre- and post-spike timings and more complicated routing compared to two-factor STDP | Loihi 2 supports programmable three-factor learning; BrainScaleS-2 provides partial support; SpiNNaker supports software implementation; TrueNorth does not support online learning. |
Figure 4:
Neuromorphic applications. AI, artificial intelligence; SLAM, simultaneous localization and mapping; SNNs, spiking neural networks.
Table 4:
Standard benchmark datasets and tasks used to evaluate neuromorphic learning and applications
| Dataset/task | What property of neural networks is tested? | Representative result | Method | Reference |
|---|---|---|---|---|
| N-MNIST | Classification task converted to spike trains by making sensor saccades; mostly static image classification, some temporal aspects included | 99.1% (ANN-to-SNN conversion); 95% (STDP, unsupervised) | ANN-to-SNN conversion; STDP | [15, 31] |
| DVS-Gesture (IBM) | Event-based stream gesture recognition (11 classes); real spatiotemporal dynamics generated by DVS camera | Accuracy of 96.5%, ∼105 ms latency, and power consumption less than 200 mW on TrueNorth | CNN running on TrueNorth (event-based) | [32] |
| DVS-Gesture (SLAYER) | Same task as DVS-Gesture above but with software-based SNN training using surrogate gradients | Accuracy of 93.64% in recognizing 11 classes (trained on GPU) | SLAYER (surrogate-gradient SNN) | [33] |
| CIFAR-10 (SNN conversion) | Image classification; used to test scalability of SNN to difficult tasks | Accuracy of ∼93.6% in deep ANN-to-SNN conversion | ANN-to-SNN conversion | [12] (ANN-to-SNN conversion methods review) |
| SHD | Spoken digit recognition; explicitly engineered to require temporal structure of spikes, not just their firing rates | Used as the standard benchmark for testing if learning rule uses temporal structure (architecture-dependent accuracy) | Recurrent SNNs, surrogate gradient, e-prop | [34] |
Table 5:
Synthesis of consensus, disagreement and uncertainty across the studies reviewed
| Topic | Where studies agree | Where studies disagree or diverge | What remains uncertain |
|---|---|---|---|
| Energy efficiency of digital event-driven chips | TrueNorth, Loihi and Loihi 2/Hala Point all report large (10x–100x -scale) energy-per-operation or energy-per-inference advantages over CPU/GPU baselines on sparse, event-driven workloads (Table 2) | The size of the reported advantage varies widely by benchmark and by which power draw is counted (dynamic-only vs dynamic + static, single-chip vs full-system), so figures are not directly comparable across studies | Whether these advantages hold on dense, large-scale AI workloads (e.g., LLM-scale models) rather than small benchmark tasks is largely unverified outside vendor characterizations (Section III g) |
| STDP as the dominant unsupervised, on-chip-compatible rule | Across Sections V and V a., STDP and its variants are consistently reported as the most widely implemented on-chip learning mechanism, on both digital (Loihi) and analog/mixed-signal (DYNAP-SE2, memristive crossbar) substrates | Studies differ on which STDP variant (pair-based, triplet, rate-based) best captures biological plausibility versus task performance; no consensus exists on a single preferred variant | How well STDP-trained networks scale to large, deep architectures—as opposed to the small, shallow networks in most published demonstrations—is not established |
| ANN-to-SNN conversion accuracy | Multiple independent studies agree that conversion can match ANN accuracy on static image-classification benchmarks (e.g., N-MNIST, CIFAR-10) when enough timesteps are used (Sections VI f.) | Studies disagree on how many timesteps are “enough”: reported saturation points range from roughly a dozen to several hundred timesteps depending on network depth, dataset and the specific calibration technique used | The latency/accuracy tradeoff at very low timestep counts (the regime most relevant to real-time edge deployment) is an active research area without a settled best practice across the studies cited here |
| Device variability in analog/memristive substrates | All sources discussing analog and memristive devices (Sections III b.iv, VII c) agree that device-to-device and cycle-to-cycle variability is a genuine, unresolved engineering obstacle, not a solved problem | Studies disagree on the most promising mitigation: calibration-heavy approaches (BrainScaleS-2) versus device-engineering approaches (transistor-free crossbars) versus algorithmic compensation (write-and-verify, piecewise-linear correction) are pursued as largely separate research programs | Whether any single mitigation generalizes from small demonstration arrays to the wafer- or system-scale integration discussed in Section III b.iii remains untested in the literature surveyed |
| Benchmarking and standardization gap | Every source in Section VIII’s literature table, independently, identifies the lack of standardized benchmarks and cross-platform comparison methodology as a top unresolved challenge (Section VII a) | No disagreement was found on whether this gap exists; sources differ mainly in which specific fix they prioritize (common benchmarks, common software interfaces or common hardware-level metrics) | No consensus benchmark suite has yet emerged from any of the proposals surveyed, so this remains an open problem rather than one with competing but resolved solutions |
| Papers | Insights | Future Research |
|---|---|---|
| This review aims to provide an integrated systematic overview of neuromorphic computing: its biological foundations, the different computational models that can be used to develop the hardware architectures and the different pieces of equipment or technologies to support these systems, as well as the various types of learning processes available within neuromorphic systems |
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| Neuromorphic computing is inspired by the structure and function of the brain, pursuing high speed, low power consumption and big data processing. It enhances AI and machine learning; at present, the development of neural computing chips faces challenges, though, and it’s in its infancy |
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| Neuromorphic computing is one such brain-inspired AI strategy that effectively replicates human neural architecture by means of SNNs and memristors. These allow for event-driven processing, contextual learning and energy efficiency while striving to enhance cognitive capabilities and ensure progress in artificial general intelligence. |
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| Neuromorphic computing represents a non-von Neumann computation inspired by brain structures that use spikes to encode data. It allows for high parallel operation, scalability and power-efficient computation, especially through SNNs, which reduce power consumption while enhancing learning capacity |
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| Neuromorphic computing is an AI methodology based on computational principles of biological brains, enabling higher energy efficiency along with performance. It employs SNNs and memristors, improves performance in tasks related to pattern recognition or adaptive learning and tackles power consumption challenges |
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| Neuromorphic computing develops the neural structures and functionalities that exist in the human brain, increasing efficiency and adaptability within AI. It allows for real-time processing, power-efficient computation and scalability while invoking material limitations and integration into existing technologies |
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| Neuromorphic computing is all about replicating the brain’s computing principles in materials and devices to, possibly, scale technology development further than with conventional architectures such as von Neumann |
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