Neuromorphic Computing: Architectures, Learning Mechanisms, Hardware Platforms and Emerging Applications

a. Review methodology and scope

The present review considers papers published up to the middle of 2025 (see Section 2.1 for details about the search process) as compared to the first version of this paper, which had been limited to publications until mid-2019 (for the literature search methodology used then). Methodology and Scope of Literature Search.

This is a narrative review, not a systematic one. Therefore, this work does not adhere to the PRISMA guidelines; that is, it does not involve any preregistration of a search query together with its screening according to strict criteria of inclusion or exclusion. Sources for this work were obtained as follows: (i) via direct search for the key terms such as “neuromorphic computing,” “spiking neural network,” “memristor,” “Loihi,” “SpiNNaker,” “TrueNorth,” “BrainScaleS” and “neuromorphic benchmark” within several academic databases including IEEE Xplore, Google Scholar, ScienceDirect and arXiv; (ii) through forward and backward citation tracking within relevant works from foundational papers (Mead, 1990; Merolla et al., 2014; Davies et al., 2018) to the latest papers quoting them or being quoted by them and (iii) via manufacturer and laboratory web pages related to specific systems (Intel Newsroom, BrainScaleS-2 documentation). Papers published since 1990 until mid-2025 were taken into account. No formal criteria for inclusion/exclusion of studies, database coverage statistics or interrater screening were used, which is appropriate to the nature of a narrative review; users who require replication of the literature search at the systematic review level should view the bibliographic references as representative of the important topics and findings in the field rather than as a formally reviewed set of studies and should be aware that the findings presented in Section IX is not a meta-analysis.

a. Platforms covered

This examination conducts a comparative analysis of six exemplary platforms that encapsulate the prevailing design paradigms in contemporary neuromorphic research and its commercialization endeavors:

• IBM TrueNorth [4] (a digital, event-driven neurosynaptic chip architecture).

• Intel Loihi/Loihi 2 (along with the Hala Point system) [2] (comprising digital, programmable spiking cores integrated with on-chip learning capabilities; Loihi 2 represents the most recent iteration of the research chip, while Hala Point constitutes an extensive Loihi-2 system).

• SpiNNaker [3] (a massively parallel ARM-based platform designed for the simulation of large-scale SNNs). Its successor, SpiNNaker 2, reached commercial availability in 2024–2025 and is discussed alongside it in wherever the two generations differ materially.

• BrainScaleS-2 [5] (an advanced mixed-signal/analog neuromorphic system that prioritizes rapid emulation of neural dynamics).

• BrainChip Akida [7] (a commercial event-domain neural processor aimed at edge AI applications).

• DYNAP family (for instance, DYNAP-SE2) [6] (a series of scalable multicore dynamic neuromorphic processors and research prototypes concentrating on asynchronous event routing methodologies).

b. Comparison axes and summary

c. Strengths, limitations and recommended match between platform and problem class

• Edge inference to conserve energy (vision, audio, IoT): When the workload consists primarily of inference, has a large degree of sparsity and requires a development pipeline to make it commercially viable, Akida and TrueNorth (digital event-driven) chips are well-suited as candidates. In contrast, digital event-driven architecture exists in a research capacity with Loihi.

• On-device continuous learning/adaptive control: With Loihi 2’s programmable on-chip learning capabilities, Loihi 2 is a powerful engine for on-device continuous learning/adaptive control. BrainScaleS provides the opportunity to test new learning rules offline using accelerated analog dynamics.

• Large-scale, biologically realistic brain simulations: SpiNNaker and large-scale clusters of Loihi are designed to handle large volumes of computational neuroscience workloads; SpiNNaker provides a complete software platform tuned specifically for computational neuroscience.

• Device-level implications of synaptic willingness/plasticity, density and energy: BrainScaleS, DYNAP/digital event-driven/mixed-signal platforms (such as memristor/mixed-signal platforms) facilitate access to new device physics but also require additional engineering to obtain reproducibility.

d. Open challenges revealed by the comparison

• Edge inference for energy savings (vision, audio and IoT): When inference makes up most of the workload and the inference has high sparsity (which requires developing a pipeline to achieve commercial viability), Akida and TrueNorth Chips (digital event-driven) are strong candidates for use. In contrast, digital event-driven architecture only exists in the research domain at this time with Loihi.

• On-device continuous learning/adaptive control: Loihi 2 is capable of on-device continuous learning through programmable learning capabilities onboard Loihi 2. BrainScaleS has facilities to run new learning rules using accelerated analog dynamics within a laboratory setting.

• Large-scale, biologically realistic brain simulations: SpiNNaker and clustered Loihi systems with high capacity to execute computational neuroscience workloads (e.g., at scale or high-throughput computing) are specifically built for computational neuroscience.

• Device-level implications of synaptic willingness/plasticity/density/energy: BrainScaleS, DYNAP/Digital Event Driven/mixed-signal platforms (e.g., memristor/mixed-signal platforms) provide access to new device physics, but there is more engineering work to achieve reproducible results.

e. Practical recommendations for researchers and practitioners

• Loihi 2 or Loihi Clusters are the best options for researchers who want more flexibility in their models and a resource to experiment with online learning.

• If you are looking for an easy way to create large SNNs that match the biological rate of computation using state-of-the-art computer networking technology, you might want to consider using SpiNNaker and its associated software environment.

• Akida and similar products are good options if your objectives are energy-efficient solutions for low-power edge computing systems.

• If you want to answer specific questions about learning, you can use the brain model BrainScaleS, or if you are interested in conducting faster simulations of learning or behavior, then use equipment that uses mixed signals, such as those on the BrainScale platform.

f. Concluding remarks

Different design tradeoffs can be made when designing major neuromorphic platforms with respect to programmability, energy, scale, device technology and support for the ecosystem; therefore, no single platform dominates on all dimensions. Each project will ultimately determine the right platform for its application depending on its use case (inference, continual learning or neuroscience simulation), current level of sophistication and available support, and its tolerance for variability in the devices used. Once toolchains have matured and standard benchmarks become established, then the research community should be in a better position to quantify the tradeoffs and codesign algorithms that take advantage of the strengths of each platform, as shown in Figure 1.

Figure 1:

g. Quantitative benchmarks and defined metrics

The qualitative comparisons made in Sections III b–III d are benchmarked against metrics here as well, so as to verify claims about the hardware’s efficiency, scalability and learnability on a quantitative level rather than in a qualitative sense. The following three categories of metrics are applied uniformly to all platforms: (i) Energy-per-operation—expressed in units of pico-joules (pJ) or milli-joules (mJ) per operation (or per synaptic event, per inference), representing the energy cost of performing a unit of computations; (ii) Throughput-per-power—expressed in giga-, tera-operations-per-second-per-watt (GSOPS/W, TOPS/W), representing a sustained computational throughput measured relative to the power required to maintain such rate and (iii) Scale—expressed in terms of neurons, synapses or cores within a single chip/system. Table 2 shows representative values of each metric category according to their respective sources; those derived from vendor sources (as noted under the column “Metric”) have not been independently verified and are reported as vendor values.

Such metrics show the magnitude of the efficiency improvements cited in the literature—for example, TrueNorth’s energy consumption per event is about four orders of magnitude lower compared to an average multiply accumulate operation on a generic CPU, and Loihi’s energy consumption for inference on a small network of keyword spotting is 15 times lower than a Cortex-M7 benchmark in the same task—but the comparisons are not always apples to apples because the measurements are taken at different tasks, using different sizes of neural networks, different process technologies and different ways of measurement (e.g., dynamic versus dynamic + static measurements, single chip versus system measurements). Therefore, the ratios of cross-platform measurements presented in Table 2 can be understood as order-of-magnitude estimates rather than precisely controlled benchmark results. In fact, measurement inconsistency is one of the key standardization issues outlined in Section VII a and the reason why efficiency and scalability statements throughout the paper are qualitative in nature.

a. Learning mechanisms mapped to hardware constraints

Each of the four learning mechanisms discussed above imposes distinct hardware requirements. Consequently, not every learning mechanism can be implemented on every neuromorphic platform described in Section 3. The compatibility between a learning rule and a hardware platform depends on the availability of the necessary architectural features, such as programmable synaptic plasticity, weight-update circuits, modulatory signal pathways, or support for external training.

Table 4 summarizes the relationship between the learning mechanisms and the surveyed hardware platforms. For each learning mechanism, it identifies the minimum hardware requirements, the platforms that support the required functionality, and whether learning is performed on-chip, where synaptic weight updates are computed locally on the hardware, or off-chip, where weight updates are computed externally and later deployed to the hardware. This distinction is important because statements such as “the hardware supports STDP” or “supports surrogate-gradient learning” may be misleading unless the underlying learning capability and its implementation are clearly specified.

There are two observations worth making here. First, biological plausibility and on-chip learning are different axes: the STDP and three-factor rules that have the highest biological plausibility are also whose weight updates rely only on locally available information and can, therefore, be implemented easily on-chip (because their update rule depends only on spike timing, and for three-factor rules—also on a locally available modulatory signal), while methods such as surrogate gradient-based learning and ANN to SNN conversion usually require either the whole network computation akin to backpropagation or offline training, which explains their mostly off-chip nature even on chips such as Loihi 2 that support flexible on-chip learning for other types of plasticity; an exception would be BrainScaleS-2’s surrogate gradient-based training in-the-loop (see Section VII c), and the reason for this is the analog chip remains part of the loop rather than being used purely as a deployment platform. The second downside is that learning-free approaches sacrifice biological realism and adaptivity in exchange for simplicity of implementation in hardware: since no learning mechanism is required whatsoever, these networks can be implemented even in such chips as TrueNorth, which does not have any general-purpose learning capabilities, but the deployed network becomes incapable of adapting without retraining. Readers who are interested in the comparison of the efficiency and accuracy numbers across the learning techniques discussed in Section V are also advised to verify from Table 3 if the comparison is made between an on-chip adaptable network and a pretrained network.

a. Edge AI and low-power inference

Neuromorphic computing is growing in popularity in various fields where low latency, efficient energy use and adaptive computing are necessary. This is largely due to the fact that spiking and event-driven systems represent an ideal way to deliver real-time sensing and embedded intelligent processing capabilities.

b. Robotics and autonomous systems

Robotics depends on real-time adaptation and comprises dynamic gait control, obstacle avoidance, simultaneous localization and mapping, and sensory fusion with support from neuromorphic systems. Closed-loop robotic tasks have been performed using both Loihi and DYNAP-SE, providing an approach to learning online and adapting to changing environments. The use of direct vision sensors and the combination of them with neuromorphic (or brain-inspired) processors provides the capability of tracking high-speed motion in real-time from the camera’s response time (∼1 μs), thereby enabling the ability of fast and flexible (agile) navigation of robots.

c. Biomedical and brain–machine interfaces

The signals produced by biological systems (EEG, EMG, Neural Spike Train) work well with neuromorphic systems. Low-power SNN architectures can use these signals to decode neural activity to predict or control a prosthetic device. Chips such as NeuroGrid (mixed signal) can produce biologically realistic simulations that can be used for neuroscience research and the study of neurological disorders. Driven Retinal Implants are examples of next-generation biomedical interface neuromorphic sensors.

d. Scientific simulation and computational neuroscience

Large-scale modeling of cortical circuits and the study of synaptic physiology are possible with platforms such as SpiNNaker and BrainScaleS. These platforms also provide information about neural computation, cognitive processes and the mechanisms behind various diseases. Rapidly prototyping new neural models is possible using time-accelerated analog systems.

e. Industrial and security applications

Industrial processes, monitoring vibrations and detecting anomalies have all been investigated with neuromorphic systems to ascertain uses for this technology. An example of their positive use would be the ability of event-driven processing to act on sparse and unpredictable data streams such as packets and system irregularities. Additionally, neuromorphic systems operate at low power consumption, making them ideal for distributed sensor network applications.

f. Benchmark datasets and tasks

The applications discussed above and the learning methods covered in Section V are compared, in the body of literature reviewed here, with respect to a small number of consistent benchmark datasets and tasks rather than with respect to each other in an abstract sense. Reference to such tasks allows assertions regarding accuracy, robustness or learning ability to be tested for and compared with each other, rather than making comparisons between fundamentally inconsistent evaluation frameworks. Table 4 lists some of the benchmark datasets often used to assess SNNs and neuromorphic systems, the quality each one is intended to measure and example findings.

These tasks serve to distinguish two assertions that tend to be confused in the literature—a large accuracy value achieved for a dataset of static images such as N-MNIST only shows the capability of a network to recognize spatial patterns, because ANNs trained on the same dataset of collapsed frames yield similar accuracy without relying on the timing of spikes; proving the unique strength of SNNs in temporal coding on the other hand necessitates datasets with real spatiotemporal properties, like DVS-Gesture or SHD, where models relying solely on spike rate or purely spatial do not perform as well. The readers must then be wary that the accuracy values given in Sections V and VI are relevant to certain benchmarks alone and not as a claim of superiority of SNNs. Just like the hardware measurements in Table 2, the lack of a required benchmark suite (refer to Section VII a.) means the numbers in Table 4 have been measured using different sizes of networks, training methods, and splitting for training and testing, and as such they should be interpreted as indicative only.

g. Frameworks for benchmarking and dataset infrastructure

Table 4 lists benchmark tasks and datasets individually, but task lists are not to be confused with evaluation frameworks, as frameworks outline the methodology, harness and definition of metrics that make comparison of results on these tasks possible at all, which is the gap identified by this review multiple times (Sections III g. and VII a, Table 5). There are two community infrastructures worth singling out here, as they cover different aspects of this gap.

a. Lack of standardized benchmarks

There is considerable variation between different platforms in how evaluation works for energy efficiency, latency, accuracy and scalability (current evaluation approaches do not have a consistent method for making comparisons across different platforms). Therefore, event-driven workloads will require unique benchmarks (distinct from currently existing AI datasets).

b. Limited software ecosystems

To program neuromorphic hardware, you need specialized frameworks and domain knowledge. Although existing initiatives, such as Nengo, Lava, PyNN and Brian2, have improved the usability of neuromorphic computing, there is still a lack of debugging tools, compilers and seamless transferability of models between different neuromorphic platforms.

This is illustrated by the differences in the support and boundaries of hardware that the four mentioned frameworks have. Nengo provides a Python API based on Neural Engineering Framework; it works with LIF and some other types of neurons, trains neural networks using its own algorithms or by means of integrating with Keras/TensorFlow-like APIs and deploys the same model description onto several backends, including CPU/GPU simulation, Loihi using NengoLoihi, SpiNNaker and FPGAs with minimal changes in code; while the interoperability of this framework is achieved at the expense of adherence to the NEF modeling style, which limits users in their freedom of modifying details of neuron and learning rule implementations. Lava, Intel’s framework for Loihi-like processors, uses the architecture of communicating processes; its Lava-DL part enables training deep SNNs using the SLAYER algorithm or converting from the ANNs trained using PyTorch, but in-chip training is not currently provided through this approach—trained off-chip and then exporting of weights into Lava are required, so training flow and deployment target become two separate phases. PyNN, in contrast, uses a simulator-independent description language for SNN models (neurons, populations, connectivity, and STDP and Hebbian-like plasticity algorithms) and allows the same script to run unchanged on NEST, Neuron, Brian2 and through hardware back-ends, SpiNNaker and BrainScaleS. The latter is PyNN’s strength and weakness because it imposes a standardized feature set across simulators and thus fails to expose any chip-specific features, such as the programmable three-factor learning algorithm available on Loihi 2. The primary application of Brian2 is as a differential equation simulation tool for computational neuroscience and not as an interoperability tool for neuromorphic chips; however, project-specific emulators such as Brian2Loihi enable running the target chip simulations using a software environment and are helpful when developing a program without hardware availability; however, it must be noted that although the published validation results show that the average change in weights is consistent between Brian2Loihi and the actual chip, the latter is not replicable due to the stochastic rounding that occurs on the actual hardware.

More broadly, interoperability usually fails at one of three common junctures among these and other tools (snnTorch, Norse, BindsNET, SNN Toolbox): the process of converting existing mainstream deep learning frameworks is well-suited to feed-forward image classification models but not to all neural network architectures since each process entails a particular target neuron model (e.g., integrate and fire or LIF) and may ignore layers that do not fit this architecture; in-chip versus out-of-chip training is not always possible, and some frameworks (e.g., Lava-DL, SNN Toolbox) require the weights of neurons to be trained elsewhere and imported, not learned on the target hardware itself; and even when there is a common modeling language, deployment becomes hardware-dependent because although PyNN code runs unchanged between simulators, it requires hardware-specific configuration when used with the different backends of SpiNNaker versus BrainScaleS, respectively. Intermediate representations that attempt to solve the issue of conversion, such as the recent NIR initiative, have been defined as a way to create a small set of hardware-independent computational elements to be targeted by various simulators and chips, but this has yet to become a reality among the frameworks discussed here, as expected from the lack of portability described above.

This issue—assessment of a complex, multicomponent system in terms of performance criteria—exists outside the neuromorphic computing realm too, and the solutions developed elsewhere may prove helpful. For example, Wang [36] proposes an index system that assesses shared computer hardware and software resources in cloud systems in terms of resource usage, response time, throughput and scalability together, then combines all these criteria using a learned model instead of evaluating them independently and providing a set of noncomparable numbers. Similarly, Jayapradha et al. [37] combine several model components into one hybrid prediction-and-visualization pipeline and evaluate the resulting system as a whole rather than individual components. Neither work considers neuromorphic hardware or spiking learning algorithms, but both demonstrate a particular methodological approach that has not become common practice in the neuromorphic software ecosystems domain yet—namely, setting a fixed multidimensional index to evaluate framework/platforms and assessing them based on the latter, which is the purpose of this subsection and Table 3.

c. Device variability in analog systems

Variability is a significant issue in analog and memristive devices, making them more complex for large-scale implementation due to variations in drift, stochastic switching, and fabrication defects. Therefore, they require very high calibration and/or compensatory error methods.

“High calibration and/or compensatory error methods,” on the other hand, refer to a particular set of experimental approaches that address specific types of failures. In relation to mismatch in time constant of neurons and chip-to-chip mismatch in the case of fabrication-induced mismatches in BrainScaleS-2, on-chip per-circuit calibration through on-chip digital-to-analog converter settings and on-chip analog-to-digital converter readings prior to experimentation are done. Results show that through this process, fixed-pattern error in neuron time constant is minimized to less than 5% of the target value and analog mismatch is reduced to 10% or less compared to significantly higher values prior to calibration. As for nonlinearity and cycle-to-cycle variations in memristive synapses, write-and-verify cycles (pulsing a device iteratively and reading its conductance until it is at the target state) and piecewise-linear compensation models are used to compensate for weight update errors in training; for example, one experiment shows that classification accuracy of digit recognition is recovered to 87.87%–95.05% in 49 simulations with different device nonlinearity. For conductance drifts on longer time scales, the prevalent mitigating technique discussed in the literature is “in-the-loop” or “hardware-in-the-loop” training, whereby the actual device or the chip is included in the loop of training (and is not trained only using simulation and then deployed) and the learning algorithm adjusts to each instance in terms of its measured performance, rather than to an idealized model of the device; surrogate-gradient training directly on the BrainScaleS-2 hardware is an example of such a technique. As for yield and reliability between devices at the array scale, transistor-less crossbar arrays discussed in the literature have exhibited a low variation with yields of up to 100% on small test arrays, although such figures are given per manufacturing batch and do not automatically guarantee reproducibility across wafers or multi-chips as discussed in Section III. Thus, reproducibility across multiple batches and devices relies on specifying which (if any) of these mitigations were used (device-level calibration, write-and-verify programming, in-the-loop training or none) along with the accuracy or efficiency of the result, because even the same learning rule can exhibit different results if device-level compensation was used or not.

d. Training complexity and accuracy gaps

Despite improvements in performance from techniques such as surrogate learning and the conversion of ANNs into SNNs, an SNN’s ability to achieve state-of-the-art performance on large benchmark datasets continues to be an obstacle. Active research continues to explore the idea of combining an ANN’s training process with SNNs’ ability to infer and learn locally by developing a hybrid architecture for them.

e. Scaling and interconnect challenges

Large neuromorphic systems require massive spike-routing bandwidth. Efficient, scalable interconnects—such as mesh networks, optical links or 3D integration—are essential for next-generation systems.

f. Toward cognitive-level systems

While current neuromorphic chips emulate network dynamics and plasticity, achieving cognitive-level behavior requires advances in memory organization, neuromodulation, hierarchical learning and multi-timescale processing.

g. Algorithm-hardware codesign: hardware-aware learning, model mapping and optimization

The concept of “codesign” is mentioned in other places in this review (Introduction; Section IV; Conclusion), but “codesign” refers to three different engineering challenges with different methods: hardware-aware learning of a model, in which a trained model is trained so that it already takes into account constraints of the target chip, model mapping, in which the model’s graph is mapped to placements of neurons and synapses to physical cores, and optimization, in which a trained model is changed in terms of its architecture or precision in order to minimize usage of resources of the target hardware.

a. Synthesis of the literature surveyed

The above table is kept for easy reference as an index of the eight surveyed articles, but on its own, it is more of an annotated bibliography rather than a synthesis since each entry essentially repeats the perspective of that paper in isolation. Looking at the eight articles collectively, three main themes emerge from them, and it is more useful to analyze these themes and how they contribute to each other rather than taking them separately.

Theme 1: General-overview papers restating the field’s established framing. Papers by Londhe et al. [21], Akib [22], Vajpayee et al. [23] and Garg [24] provide a review-level summary of neuromorphic computing in terms of its biological inspiration, SNN/memristor-based technology and energy-efficient potential, just like the introduction part of the current paper does. The utility of those papers lies in the fact that they serve as evidence for the consensus framing employed in this review (event-driven nature of the calculations, in-memory computations, use of spikes as the basis for efficiency) and not in introducing a different framing. None of those papers introduces any quantitative information beyond what was provided in the tables in this paper (Tables 1, 2 and 4), and their suggestions for future research (standards for interoperability, hardware variability, software tools) are just repetitions of the challenges listed in Section VII.

Theme 2: SNN learning-capacity and hybrid-architecture papers. Gangshettiwar et al. [25] and Malviya et al. [26] both name the learning capacity of SNNs and the hybrid ANN and SNN architecture as the priority direction of research, corroborating, independently of one another, the discussion in Sections V and of this paper of surrogate gradient-based learning, e-prop and ANN-to-SNN conversion. Their value lies in showing that this is a well-recognized priority independent of the particular hardware vendor or research lab, bolstering the case for the stated consensus of Table 5’s rows on STDP and conversion accuracy; none of these papers, however, add any new benchmark information beyond that already included in Table 3.

Theme 3: Materials and fabrication-level challenges. Both Elfighi [27] and Hunagund [28] focus on the limits imposed by device and material properties—charge and defect mobility, manufacturing and fault tolerance—as being the key constraint on the scalability of neuromorphic devices, which is the same conclusion reached by this review in an independent way in Section VII c. When taken with Section VII c, the two papers suggest that there is awareness of the variability problem at both the level of device physics and system calibration, but as distinct problems, which is helpful but does not, on its own, answer the open question raised in Table 5 of whether any particular approach is scalable from laboratory demonstration to mass manufacturing.

In all three topics, a common trend can be observed: these eight papers, for the most part, simply reconfirm what is found in this review in more detail elsewhere (Sections V–VII, Table 5) via separate authorship, rather than provide any evidence that would change these results. Hence, the contribution of this table to the body of evidence should be regarded as its breadth of corroboration—that the open questions in this field are known widely, not just by a few authors—rather than as its depth of evidence.

b. Overcoming current challenges

Standardization and Interoperability: The future should seek to develop standardized methods which would ensure compatibility and interoperability among different neuromorphic systems 1. This involves developing common benchmarks through which such platforms can be compared effectively; the current evaluation methods largely remain very different across different platforms with respect to energy efficiency, latency, accuracy and scalability 2. Event-driven workloads will require unique benchmarks different from the datasets that already exist in AI applications 2.

Addressing Hardware Variability: Hardware variability in analog and memristive devices should be addressed to reinforce the reliability and performance of neuromorphic systems [1, 3]. The variability occurring due to drift, stochastic switching and fabrication defects implies that complex and large-scale integrations are challenging with high calibration or compensatory error methods [3].

Software Tool Development: Advanced software tools are a priority that will enable the programming and use of neuromorphic architectures more conveniently [1]. While efforts such as Nengo, Lava and PyNN have increased usability, there remains a need for debugging tools, compilers and seamless transferability of models across different platforms [4].

c. Enhancing learning and performance

Improving Learning Capacity of SNNs: Future research needs to be directed to improve the learning capability of SNNs, which will further enhance performance in various application scenarios [5]. This may involve exploring methods for optimizing power consumption in neuromorphic computing systems [5].

Hybrid Architectures and Algorithms: Active research is underway to explore the combination of the training process of artificial neural networks with the capability of SNNs to make inferences and learn locally by developing hybrid architectures [6]. Hybridization of biological local rules with surrogate gradient descent and reinforcers will further enhance neuromorphic systems for adaptable behaviors, autonomous environmental detection and continuous learning [7].

d. Expanding application areas

Scalability in Real-World Scenarios: The scalability of SNNs can be explored in larger and more complex systems to gain insights into their practical applications in real-world scenarios [5].

Integration with Currently Available Technologies: The research will probe the integration of neuromorphic computing into the existing AI frameworks to enhance energy efficiency and real-time adaptability [8]. This will provide advanced capabilities to AI systems [9].

Specific Application Domains: Future work on neuromorphic systems in various application domains such as healthcare, transportation, robotics, edge computing and brain–machine interfaces is needed to bring significant technological advancements in support of human capabilities [1, 8, 10].