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Design and Performance Testing of a Simulation Model for Time-Triggered Ethernet Cover

Design and Performance Testing of a Simulation Model for Time-Triggered Ethernet

International Journal of Advanced Network, Monitoring and Controls
Volume 8 (2023): Issue 3 (September 2023)
By: Bidong Duan and  Jing Cheng  
Open Access
|Mar 2024

Figures & Tables

Figure 1.

TTEthernet Overall Model
TTEthernet Overall Model

Figure 2.

TTEthernet End System Simulation Model
TTEthernet End System Simulation Model

Figure 3.

Three types of jitter situations
Three types of jitter situations

Figure 4.

Triple Redundancy Network Architecture
Triple Redundancy Network Architecture

Figure 5.

TTEthernet Switch Simulation Mode
TTEthernet Switch Simulation Mode

Figure 6.

Ping-Pong buffer operation structure
Ping-Pong buffer operation structure

Figure 7.

CrossBar Switching Matrix
CrossBar Switching Matrix

Figure 8.

TTEthernet Simulation System Timing Diagram
TTEthernet Simulation System Timing Diagram

Figure 9.

TTEthernet topology
TTEthernet topology

Figure 10.

Simulation configuration information
Simulation configuration information

Figure 11.

Throughput of TTEthernet simulation system
Throughput of TTEthernet simulation system

Figure 12.

End-to-End Delay of three types of messages
End-to-End Delay of three types of messages

Figure 13.

Packet loss rates for three types of messages
Packet loss rates for three types of messages
DOI: https://doi.org/10.2478/ijanmc-2023-0066 | Journal eISSN: 2470-8038
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Language: English
Page range: 57 - 66
Published on: Mar 15, 2024
Published by: Xi’an Technological University
In partnership with: Paradigm Publishing Services
Publication frequency: 4 issues per year
Keywords:
Time-Triggered Ethernet,
Simulation Model,
Switching Architecture,
OPNET
Related subjects:
Computer sciences,
Computer sciences, other

© 2024 Bidong Duan, Jing Cheng, published by Xi’an Technological University
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.

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