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Design and Performance Testing of a Simulation Model for Time-Triggered Ethernet Cover

Design and Performance Testing of a Simulation Model for Time-Triggered Ethernet

By: Bidong Duan and  Jing Cheng  
Open Access
|Mar 2024

Figures & Tables

Figure 1.

TTEthernet Overall Model

Figure 2.

TTEthernet End System Simulation Model

Figure 3.

Three types of jitter situations

Figure 4.

Triple Redundancy Network Architecture

Figure 5.

TTEthernet Switch Simulation Mode

Figure 6.

Ping-Pong buffer operation structure

Figure 7.

CrossBar Switching Matrix

Figure 8.

TTEthernet Simulation System Timing Diagram

Figure 9.

TTEthernet topology

Figure 10.

Simulation configuration information

Figure 11.

Throughput of TTEthernet simulation system

Figure 12.

End-to-End Delay of three types of messages

Figure 13.

Packet loss rates for three types of messages
Language: English
Page range: 57 - 66
Published on: Mar 15, 2024
In partnership with: Paradigm Publishing Services
Publication frequency: 4 issues per year

© 2024 Bidong Duan, Jing Cheng, published by Xi’an Technological University
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.