Spiking Neural Network Based on Cusp Catastrophe Theory

Huderek, Damian; Szczęsny, Szymon; Rato, Raul

doi:10.2478/fcds-2019-0014

Abstract

This paper addresses the problem of effective processing using third generation neural networks. The article features two new models of spiking neurons based on the cusp catastrophe theory. The effectiveness of the models is demonstrated with an example of a network composed of three neurons solving the problem of linear inseparability of the XOR function. The proposed solutions are dedicated to hardware implementation using the Edge computing strategy. The paper presents simulation results and outlines further research direction in the field of practical applications and implementations using nanometer CMOS technologies and the current processing mode.

References

[1] Chen D. D., Chen X. J., Zhang K., An Exploratory Statistical Cusp Catastrophe Model, IEEE International Conference on Data Science and Advanced Analytics, pp. 100-109, 2016.10.1109/DSAA.2016.17
Search in Google Scholar Back to article
[2] Cheng H.-P. et al., Understanding the design of IBM neurosynaptic system and its tradeoffs: A user perspective, Design, Automation & Test in Europe Conference & Exhibition, IEEE, 2017.10.23919/DATE.2017.7926972
Search in Google Scholar Back to article
[3] Davis M. et al, Loihi, Neuromorphic Manycore Processor with On-Chip Learning, IEEE Micro, vol. 38, Issue 1, pp. 82-99, 2018.10.1109/MM.2018.112130359
Search in Google Scholar Back to article
[4] Enríquez-Gaytán J., Gómez-Castañeda F., Moreno-Cadenas J.A., Flores-Nava L.M., Experimental Spiking Neural Network: Solving the XOR Paradigm with Metaheuristics, 15th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE) Mexico City, Mexico, 2018.10.1109/ICEEE.2018.8533911
Search in Google Scholar Back to article
[5] Esposito C., Castiglione A., Pop F., Choo K. R., Challenges of Connecting Edge and Cloud Computing: A Security and Forensic Perspective, IEEE Cloud Computing, vol. 4, no. 2, pp. 13-17, March-April 2017.10.1109/MCC.2017.30
Search in Google Scholar Back to article
[6] Frenkel Ch. et al., A 0.086-mm2 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28 nm CMOS, IEEE Transactions on Biomedical Circuits and Systems, 2018.
Search in Google Scholar Back to article
[7] Luo Q. Fu, Y., Liu J., Qiu J. Bi, S., Cao Y., Ding X., Improving Learning Algorithm Performance for Spiking Neural Networks, 17th IEEE International Conference on Communication Technology, 2017.
Search in Google Scholar Back to article
[8] Hodgkin A. L., Huxley A. F., A quantitative description of membrane current and its application to conduction and excitation in nerve, The Journal of Physiology, vol. 117, pp. 500-544, 1952.10.1113/jphysiol.1952.sp004764139241312991237
Search in Google Scholar Back to article
[9] Chang R. Hu, S., Wang H., Huang J. He, Q., Efficient Multispike Learning for Spiking Neural Networks Using Probability-Modulated Timing Method, IEEE Transactions on Neural Networks and Learning Systems, 2018.
Search in Google Scholar Back to article
[10] Izhikevich E. M., Simple Model of Spiking Neurons, IEEE Transactions on Neural Networks, vol. 14, no. 6, pp. 1569-1572, 2003.10.1109/TNN.2003.820440
Search in Google Scholar Back to article
[11] Jain R., Tata S., Cloud to Edge: Distributed Deployment of Process-Aware IoT Applications, 2017 IEEE International Conference on Edge Computing (EDGE), Honolulu, HI, 2017, pp. 182-189.10.1109/IEEE.EDGE.2017.32
Search in Google Scholar Back to article
[12] Joubert A., Belhadj B., Temam O., Héliot R., Hardware spiking neurons design: analog or digital?, The 2012 International Joint Conference on Neural Networks.10.1109/IJCNN.2012.6252600
Search in Google Scholar Back to article
[13] Rato R., Coito F., Spike HW Computing, Champalimaud NeuroScience Symposium, 2013, DOI: 10.13140/2.1.3802.2723.
Search in Google Scholar Back to article
[14] Reljan-Delaney M., Wall J., Solving the Linearly Inseparable XOR Problem with Spiking Neural Networks, Computing Conference 2017, 2017.10.1109/SAI.2017.8252173
Search in Google Scholar Back to article
[15] Sourikopoulos I., Hedayat S., Loyez Ch., Danneville1 F., Hoel V., Mercier E., Cappy A., A 4-fJ/Spike Artificial Neuron in 65 nm CMOS Technology, Frontiers in Neuroscience, 2017.10.3389/fnins.2017.00123535127228360831
Search in Google Scholar Back to article
[16] Szczęsny S., Current-Mode FPAA with CMRR Elimination and Low Sensitivity to Mismatch, Circuits, Systems and Signal Processing, vol. 36, Issue 7, pp. 2672-2696, 2017.10.1007/s00034-016-0449-6
Search in Google Scholar Back to article
[17] Szczęsny S., High Speed and Low Sensitive Current-Mode CMOS Perceptron, Microelectronic Engineering, vol. 165, pp. 41-51, 2016.10.1016/j.mee.2016.08.010
Search in Google Scholar Back to article
[18] Wu X., Saxena V., Zhu K., Balagopal S., A CMOS Spiking Neuron for Brain-Inspired Neural Networks with Resistive Synapses and In-Situ Learning, IEEE Transatcions on Circuits and Systems II: Express Briefs, vol. 62, Issue 11, 2015.10.1109/TCSII.2015.2456372
Search in Google Scholar Back to article
[19] Zapata M., Balaji U. K., Madrenas J., PSoC-Based Real-Time Data Acquisition for a Scalable Spiking Neural Network Hardware Architecture, IEEE Third Ecuador Technical Chapters Meeting, pp. 1-6, 2018.10.1109/ETCM.2018.8580286
Search in Google Scholar Back to article
[20] Zhang M., Qu H., Belatreche A., Chen Y., Yi Z., A Highly Effective and Robust Membrane Potential-Driven Supervised Learning Method for Spiking Neurons, IEEE Transactions on Neural Networks and Learning Systems, vol. 30, Issue 1, pp. 123-137, 2019.10.1109/TNNLS.2018.283307729993588
Search in Google Scholar Back to article