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Hardware Reduction for Lut–Based Mealy FSMs Cover

Hardware Reduction for Lut–Based Mealy FSMs

International Journal of Applied Mathematics and Computer Science
Volume 28 (2018): Issue 3 (September 2018)
By: Alexander Barkalov,  Larysa Titarenko and  Kamil Mielcarek  
Open Access
|Oct 2018

Authors

Alexander Barkalov

A.Barkalov@imei.uz.zgora.pl

Institute of Metrology, Electronics and Computer Science University of Zielona Góra, ul. prof. Z. Szafrana 2,, Zielona Góra, Poland

Larysa Titarenko

L.Titarenko@imei.uz.zgora.pl

Institute of Metrology, Electronics and Computer Science University of Zielona Góra, ul. prof. Z. Szafrana 2,, Zielona Góra, Poland

Kamil Mielcarek

K.Mielcarek@imei.uz.zgora.pl

Institute of Metrology, Electronics and Computer Science University of Zielona Góra, ul. prof. Z. Szafrana 2,, Zielona Góra, Poland
DOI: https://doi.org/10.2478/amcs-2018-0046 | Journal eISSN: 2083-8492 | Journal ISSN: 1641-876X
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Language: English
Page range: 595 - 607
Submitted on: Oct 9, 2017
Accepted on: Apr 28, 2018
Published on: Oct 3, 2018
Published by: University of Zielona Góra
In partnership with: Paradigm Publishing Services
Publication frequency: 4 issues per year
Keywords:
Mealy FSM,
synthesis,
FPGA,
LUT,
partition,
encoding collections of output variables
Related subjects:
Mathematics,
Applied mathematics

© 2018 Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, published by University of Zielona Góra
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.

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